Home
last modified time | relevance | path

Searched refs:rd (Results 1 - 11 of 11) sorted by relevance

/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
H A Dassembler_aarch64.h310 void Mov(const Register &rd, const Immediate &imm);
311 void Mov(const Register &rd, const Register &rm);
312 void Movz(const Register &rd, uint64_t imm, int shift);
313 void Movk(const Register &rd, uint64_t imm, int shift);
314 void Movn(const Register &rd, uint64_t imm, int shift);
315 void Orr(const Register &rd, const Register &rn, const LogicalImmediate &imm);
316 void Orr(const Register &rd, const Register &rn, const Operand &operand);
317 void And(const Register &rd, const Register &rn, const Operand &operand);
318 void Ands(const Register &rd, const Register &rn, const Operand &operand);
319 void And(const Register &rd, cons
[all...]
H A Dassembler_aarch64.cpp381 void AssemblerAarch64::Mov(const Register &rd, const Immediate &imm) in Mov() argument
383 ASSERT_PRINT(!rd.IsSp(), "sp can't load immediate, please use add instruction"); in Mov()
388 unsigned int regSize = rd.IsW() ? RegWSize : RegXSize; in Mov()
401 EmitMovInstruct(rd, immValue, allOneHalfWords, allZeroHalfWords); in Mov()
408 Orr(rd, Register(Zero), orrImm); in Mov()
413 EmitMovInstruct(rd, immValue, allOneHalfWords, allZeroHalfWords); in Mov()
432 Orr(rd, Register(Zero), zeroImm); in Mov()
434 Orr(rd, Register(Zero), oneImm); in Mov()
436 Orr(rd, Register(Zero), replicateImm); in Mov()
439 Movk(rd, movkIm in Mov()
459 Mov(const Register &rd, const Register &rm) Mov() argument
503 TrySequenceOfOnes(const Register &rd, uint64_t imm) TrySequenceOfOnes() argument
570 TryReplicateHWords(const Register &rd, uint64_t imm) TryReplicateHWords() argument
620 EmitMovInstruct(const Register &rd, uint64_t imm, unsigned int allOneHWords, unsigned int allZeroHWords) EmitMovInstruct() argument
658 Movz(const Register &rd, uint64_t imm, int shift) Movz() argument
663 Movk(const Register &rd, uint64_t imm, int shift) Movk() argument
668 Movn(const Register &rd, uint64_t imm, int shift) Movn() argument
673 MovWide(uint32_t op, const Register &rd, uint64_t imm, int shift) MovWide() argument
682 Orr(const Register &rd, const Register &rn, const LogicalImmediate &imm) Orr() argument
687 And(const Register &rd, const Register &rn, const LogicalImmediate &imm) And() argument
692 Ands(const Register &rd, const Register &rn, const LogicalImmediate &imm) Ands() argument
697 Orr(const Register &rd, const Register &rn, const Operand &operand) Orr() argument
703 And(const Register &rd, const Register &rn, const Operand &operand) And() argument
709 Ands(const Register &rd, const Register &rn, const Operand &operand) Ands() argument
715 BitWiseOpImm(BitwiseOpCode op, const Register &rd, const Register &rn, uint64_t imm) BitWiseOpImm() argument
721 BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand) BitWiseOpShift() argument
730 Lsl(const Register &rd, const Register &rn, const Register &rm) Lsl() argument
736 Lsr(const Register &rd, const Register &rn, const Register &rm) Lsr() argument
742 Ubfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms) Ubfm() argument
752 Bfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms) Bfm() argument
762 Lsr(const Register &rd, const Register &rn, unsigned shift) Lsr() argument
777 Add(const Register &rd, const Register &rn, const Operand &operand) Add() argument
795 Adds(const Register &rd, const Register &rn, const Operand &operand) Adds() argument
808 Sub(const Register &rd, const Register &rn, const Operand &operand) Sub() argument
826 Subs(const Register &rd, const Register &rn, const Operand &operand) Subs() argument
852 AddSubImm(AddSubOpCode op, const Register &rd, const Register &rn, bool setFlags, uint64_t imm) AddSubImm() argument
870 AddSubReg(AddSubOpCode op, const Register &rd, const Register &rn, bool setFlags, const Operand &operand) AddSubReg() argument
892 Cmp(const Register &rd, const Operand &operand) Cmp() argument
894 Subs(Register(Zero, rd.GetType()), rd, operand); Cmp() local
897 CMov(const Register &rd, const Register &rn, const Operand &operand, Condition cond) CMov() argument
[all...]
/arkcompiler/runtime_core/static_core/static_linker/
H A Dlinker_context_misc.cpp278 auto rd = panda_file::File::Open(f); in Read() local
279 if (rd == nullptr) { in Read()
283 auto reader = &readers_.emplace_front(std::move(rd)); in Read()
/arkcompiler/runtime_core/static_core/compiler/tests/
H A Dlive_registers_test.cpp288 auto rd = graph->GetRegisters(); in TEST_F() local
290 DataType::IsFloatType(li->GetType()) ? rd->GetCallerSavedVRegMask() : rd->GetCallerSavedRegMask(); in TEST_F()
H A Dreg_alloc_linear_scan_test.cpp1476 auto rd = graph->GetRegisters(); in TEST_F() local
1478 DataType::IsFloatType(li->GetType()) ? rd->GetCallerSavedVRegMask() : rd->GetCallerSavedRegMask(); in TEST_F()
/arkcompiler/runtime_core/static_core/plugins/ets/runtime/
H A Dets_vm.h399 std::random_device rd; in InitializeRandomEngine() local
400 randomEngine_.emplace(rd()); in InitializeRandomEngine()
/arkcompiler/ets_frontend/test/scripts/auto_xts_test/
H A Drun.bat37 if exist result (rd /s /q result)
/arkcompiler/ets_frontend/ets2panda/util/
H A Doptions.cpp183 std::random_device rd; in GenerateEvaluationWrapper() local
185 ss << EVAL_PREFIX << fileBaseName << '_' << rd() << EVAL_SUFFIX; in GenerateEvaluationWrapper()
/arkcompiler/ets_runtime/ecmascript/tests/
H A Dtagged_hash_array_test.cpp404 std::random_device rd; in HWTEST_F_L0() local
405 std::mt19937 gen(rd()); in HWTEST_F_L0()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/
H A Daarch64_obj_emitter.cpp746 RegOperand &rd = static_cast<RegOperand &>(insn.GetOperand(kInsnFirstOpnd + index));
749 if (rd.GetRegisterNumber() == RSP || rn.GetRegisterNumber() == RSP) {
/arkcompiler/ets_frontend/es2panda/test/compiler/js/
H A Dcocos_worker_test.js25130 function rd(t) {
25192 backInOut: rd,
25294 [vd.BACK_IN_OUT]: rd,
[all...]

Completed in 42 milliseconds