Lines Matching refs:rd
381 void AssemblerAarch64::Mov(const Register &rd, const Immediate &imm)
383 ASSERT_PRINT(!rd.IsSp(), "sp can't load immediate, please use add instruction");
388 unsigned int regSize = rd.IsW() ? RegWSize : RegXSize;
401 EmitMovInstruct(rd, immValue, allOneHalfWords, allZeroHalfWords);
408 Orr(rd, Register(Zero), orrImm);
413 EmitMovInstruct(rd, immValue, allOneHalfWords, allZeroHalfWords);
432 Orr(rd, Register(Zero), zeroImm);
434 Orr(rd, Register(Zero), oneImm);
436 Orr(rd, Register(Zero), replicateImm);
439 Movk(rd, movkImm, shift);
444 EmitMovInstruct(rd, immValue, allOneHalfWords, allZeroHalfWords);
448 if (regSize == RegXSize && TryReplicateHWords(rd, realImm)) {
452 if (regSize == RegXSize && TrySequenceOfOnes(rd, realImm)) {
455 EmitMovInstruct(rd, immValue, allOneHalfWords, allZeroHalfWords);
459 void AssemblerAarch64::Mov(const Register &rd, const Register &rm)
461 if (rd.IsSp() || rm.IsSp()) {
462 Add(rd, rm, Operand(Immediate(0)));
464 Orr(rd, Register(Zero), Operand(rm));
503 bool AssemblerAarch64::TrySequenceOfOnes(const Register &rd, uint64_t imm)
562 Orr(rd, rd, LogicalImmediate::Create(orrImm, RegXSize));
563 Movk(rd, (imm >> firstMovkShift) & HWORD_MASK, firstMovkShift);
565 Movk(rd, (imm >> secondMovkShift) & HWORD_MASK, secondMovkShift);
570 bool AssemblerAarch64::TryReplicateHWords(const Register &rd, uint64_t imm)
591 Orr(rd, rd, orrImm);
602 Movk(rd, imm16, shift);
614 Movk(rd, imm16, shift);
620 void AssemblerAarch64::EmitMovInstruct(const Register &rd, uint64_t imm,
639 Movn(rd, imm16, firstshift);
642 Movz(rd, imm16, firstshift);
654 Movk(rd, imm16, firstshift);
658 void AssemblerAarch64::Movz(const Register &rd, uint64_t imm, int shift)
660 MovWide(MoveOpCode::MOVZ, rd, imm, shift);
663 void AssemblerAarch64::Movk(const Register &rd, uint64_t imm, int shift)
665 MovWide(MoveOpCode::MOVK, rd, imm, shift);
668 void AssemblerAarch64::Movn(const Register &rd, uint64_t imm, int shift)
670 MovWide(MoveOpCode::MOVN, rd, imm, shift);
673 void AssemblerAarch64::MovWide(uint32_t op, const Register &rd, uint64_t imm, int shift)
677 uint32_t code = Sf(!rd.IsW()) | op | imm_field | hw_field | Rd(rd.GetId());
682 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const LogicalImmediate &imm)
684 BitWiseOpImm(ORR_Imm, rd, rn, imm.Value());
687 void AssemblerAarch64::And(const Register &rd, const Register &rn, const LogicalImmediate &imm)
689 BitWiseOpImm(AND_Imm, rd, rn, imm.Value());
692 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const LogicalImmediate &imm)
694 BitWiseOpImm(ANDS_Imm, rd, rn, imm.Value());
697 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand)
700 BitWiseOpShift(ORR_Shift, rd, rn, operand);
703 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand)
706 BitWiseOpShift(AND_Shift, rd, rn, operand);
709 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand)
712 BitWiseOpShift(ANDS_Shift, rd, rn, operand);
715 void AssemblerAarch64::BitWiseOpImm(BitwiseOpCode op, const Register &rd, const Register &rn, uint64_t imm)
717 uint32_t code = Sf(!rd.IsW()) | op | imm | Rn(rn.GetId()) | Rd(rd.GetId());
721 void AssemblerAarch64::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand)
725 uint32_t code = Sf(!rd.IsW()) | op | shift_field | Rm(operand.Reg().GetId()) |
726 shift_amount | Rn(rn.GetId()) | Rd(rd.GetId());
730 void AssemblerAarch64::Lsl(const Register &rd, const Register &rn, const Register &rm)
732 uint32_t code = Sf(!rd.IsW()) | LSL_Reg | Rm(rm.GetId()) | Rn(rn.GetId()) | Rd(rd.GetId());
736 void AssemblerAarch64::Lsr(const Register &rd, const Register &rn, const Register &rm)
738 uint32_t code = Sf(!rd.IsW()) | LSR_Reg | Rm(rm.GetId()) | Rn(rn.GetId()) | Rd(rd.GetId());
742 void AssemblerAarch64::Ubfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
744 bool sf = !rd.IsW();
748 uint32_t code = Sf(sf) | UBFM | n | immr_field | imms_field | Rn(rn.GetId()) | Rd(rd.GetId());
752 void AssemblerAarch64::Bfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
754 bool sf = !rd.IsW();
758 uint32_t code = Sf(sf) | BFM | n | immr_field | imms_field | Rn(rn.GetId()) | Rd(rd.GetId());
762 void AssemblerAarch64::Lsr(const Register &rd, const Register &rn, unsigned shift)
765 if (rd.IsW()) {
774 Ubfm(rd, rn, shift, imms);
777 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand)
782 AddSubImm(SUB_Imm, rd, rn, false, -1 * imm);
784 AddSubImm(ADD_Imm, rd, rn, false, imm);
788 AddSubReg(ADD_Shift, rd, rn, false, operand);
790 AddSubReg(ADD_Extend, rd, rn, false, operand);
795 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand)
798 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue());
801 AddSubReg(ADD_Shift, rd, rn, true, operand);
803 AddSubReg(ADD_Extend, rd, rn, true, operand);
808 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand)
813 AddSubImm(ADD_Imm, rd, rn, false, -1 * imm);
815 AddSubImm(SUB_Imm, rd, rn, false, imm);
819 AddSubReg(SUB_Shift, rd, rn, false, operand);
821 AddSubReg(SUB_Extend, rd, rn, false, operand);
826 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand)
829 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue());
832 AddSubReg(SUB_Shift, rd, rn, true, operand);
834 AddSubReg(SUB_Extend, rd, rn, true, operand);
852 void AssemblerAarch64::AddSubImm(AddSubOpCode op, const Register &rd, const Register &rn, bool setFlags, uint64_t imm)
866 uint32_t code = Sf(!rd.IsW()) | op | flags_field | shift_field | imm_field | Rd(rd.GetId()) | Rn(rn.GetId());
870 void AssemblerAarch64::AddSubReg(AddSubOpCode op, const Register &rd, const Register &rn,
879 code = Sf(!rd.IsW()) | op | flags_field | shift_field | Rm(operand.Reg().GetId()) |
880 shift_amount | Rn(rn.GetId()) | Rd(rd.GetId());
886 code = Sf(!rd.IsW()) | op | flags_field | Rm(operand.Reg().GetId()) | extend_field |
887 extend_shift | Rn(rn.GetId()) | Rd(rd.GetId());
892 void AssemblerAarch64::Cmp(const Register &rd, const Operand &operand)
894 Subs(Register(Zero, rd.GetType()), rd, operand);
897 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Condition cond)
901 uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | Rd(rd.GetId());