/third_party/mesa3d/src/util/tests/ |
H A D | register_allocate_test.cpp | 99 int vreg = next_vreg++; in TEST_F() local 108 int vreg = next_vreg++; in TEST_F() local 117 int vreg = next_vreg++; in TEST_F() local [all...] |
/third_party/mesa3d/src/imagination/rogue/ |
H A D | rogue_regalloc.c | 209 const uint32_t *vreg = entry->key; in rogue_ra_alloc() local 263 uint32_t vreg = *(uint32_t *)entry->key; rogue_ra_alloc() local [all...] |
H A D | rogue_operand.h | 134 } vreg; member
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/third_party/node/deps/v8/src/compiler/backend/ |
H A D | instruction-scheduler.cc | 187 int32_t vreg = UnallocatedOperand::cast(input)->virtual_register(); in AddInstruction() local
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H A D | spill-placer.cc | 264 SetSpillRequired(InstructionBlock* block, int vreg, RpoNumber top_start_block) SetSpillRequired() argument 282 SetDefinition(RpoNumber block, int vreg) SetDefinition() argument 465 CommitSpill(int vreg, InstructionBlock* predecessor, InstructionBlock* successor) CommitSpill() argument [all...] |
H A D | register-allocator-verifier.h | 99 void AddAlias(int vreg) { aliases_.insert(vreg); } in AddAlias() argument 251 void AddDelayedAssessment(InstructionOperand op, int vreg) { in AddDelayedAssessment() argument
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H A D | instruction-selector-impl.h | 242 InstructionOperand DefineSameAsFirstForVreg(int vreg) { in DefineSameAsFirstForVreg() argument 246 InstructionOperand DefineAsRegistertForVreg(int vreg) { in DefineAsRegistertForVreg() argument 250 InstructionOperand UseRegisterForVreg(int vreg) { in UseRegisterForVreg() argument
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H A D | register-allocator-verifier.cc | 172 int vreg = unallocated->virtual_register(); in BuildConstraint() local 608 int vreg = pair.second; in VerifyGapMoves() local
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H A D | register-allocator.h | 960 int vreg() const { return vreg_; } in vreg() function in v8::internal::compiler::RegisterAllocationFlag::LiveRange::final
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H A D | instruction-selector.cc | 328 int vreg = phi->operands()[i]; in UpdateRenamesInPhi() local 352 int vreg = unalloc->virtual_register(); in TryRename() local 360 int vreg = GetVirtualRegister(node); in SetRename() local [all...] |
H A D | mid-tier-register-allocator.cc | 267 bool TryDeferSpillOutputUntilEntry(int vreg) { in TryDeferSpillOutputUntilEntry() argument 376 int vreg() const { return vreg_; } in vreg() function in v8::internal::compiler::final [all...] |
H A D | register-allocator.cc | 811 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument 2243 int vreg = unalloc->virtual_register(); ProcessInstructions() local 4888 int vreg = *it; ResolveControlFlow() local [all...] |
/third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
H A D | sfn_optimizer.cpp | 543 RegisterVec4& vreg; member in r600::ReplaceConstSource
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/third_party/mesa3d/src/gallium/drivers/r600/sb/ |
H A D | sb_bc_finalize.cpp | 516 unsigned vreg = v->gpr.sel(); in copy_fetch_src() local 623 unsigned vreg = v->gpr.sel(); in finalize_fetch() local 670 unsigned vreg = v->gpr.sel(); in finalize_fetch() local 747 unsigned vreg in finalize_cf() local 799 unsigned vreg = v->gpr.sel(); finalize_cf() local 833 unsigned vreg = v->gpr.sel(); finalize_cf() local [all...] |
/third_party/node/deps/v8/src/codegen/x64/ |
H A D | assembler-x64-inl.h | 188 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument 201 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument 210 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, Operand rm, in emit_vex_prefix() argument 223 void Assembler::emit_vex_prefix(Register reg, Register vreg, Operand rm, in emit_vex_prefix() argument [all...] |
H A D | assembler-x64.cc | 3874 void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) { in bmi1q() argument 3882 void Assembler::bmi1q(byte op, Register reg, Register vreg, Operand rm) { in bmi1q() argument 3890 void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) { in bmi1l() argument 3898 void Assembler::bmi1l(byte op, Register reg, Register vreg, Operand rm) { in bmi1l() argument 4026 void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2q() argument 4035 bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm) bmi2q() argument 4044 bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm) bmi2l() argument 4053 bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm) bmi2l() argument 4065 Register vreg = Register::from_code(0); // VEX.vvvv unused rorxq() local 4076 Register vreg = Register::from_code(0); // VEX.vvvv unused rorxq() local 4087 Register vreg = Register::from_code(0); // VEX.vvvv unused rorxl() local 4098 Register vreg = Register::from_code(0); // VEX.vvvv unused rorxl() local [all...] |
/third_party/node/deps/v8/src/compiler/ |
H A D | graph-visualizer.cc | 722 int vreg = range->vreg(); in PrintLiveRangeChain() local 1017 int vreg = top_level_live_range_json.range_.vreg(); in operator <<() local 729 PrintLiveRange(const LiveRange* range, const char* type, int vreg) PrintLiveRange() argument 1138 int vreg = ConstantOperand::cast(op)->virtual_register(); operator <<() local 1140 os << "\\"text\\": \\"v" << vreg << "\\","; operator <<() local [all...] |
/third_party/vixl/test/aarch64/ |
H A D | test-utils-aarch64.cc | 212 Equal128(uint64_t expected_h, uint64_t expected_l, const RegisterDump* core, const VRegister& vreg) Equal128() argument 291 Equal64(uint64_t expected, const RegisterDump* core, const VRegister& vreg) Equal64() argument
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/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
H A D | gpir.h | 190 } vreg; member
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/third_party/node/deps/v8/src/codegen/ia32/ |
H A D | assembler-ia32.cc | 3111 void Assembler::bmi1(byte op, Register reg, Register vreg, Operand rm) { in bmi1() argument 3146 void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2() argument 3158 Register vreg = Register::from_code(0); // VEX.vvvv unused in rorx() local 3254 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp, in emit_vex_prefix() argument 3267 void Assembler::emit_vex_prefix(Register vreg, VectorLengt argument [all...] |
/third_party/node/deps/v8/src/execution/arm64/ |
H A D | simulator-arm64.h | 1003 T vreg(unsigned code) const { in vreg() function in v8::internal::Simulator 1013 inline SimVRegister& vreg(unsigned code) { return vregisters_[code]; } in vreg() function in v8::internal::Simulator 1039 T vreg(unsigned size, unsigned code) const { vreg() function in v8::internal::Simulator [all...] |