| /third_party/node/deps/v8/src/interpreter/ |
| H A D | interpreter-assembler.h | 88 RegListNodePair(TNode<IntPtrT> base_reg_location, TNode<Word32T> reg_count) in RegListNodePair() argument
91 TNode<Word32T> reg_count() const { return reg_count_; } in reg_count() function in v8::internal::interpreter::InterpreterAssembler::RegListNodePair
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| H A D | interpreter-assembler.cc | 264 TNode<Uint32T> reg_count = BytecodeOperandCount(operand_index + 1); in GetRegisterListAtOperandIndex() local
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| /third_party/skia/third_party/externals/spirv-tools/source/opt/ |
| H A D | register_pressure.cpp | 217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/ |
| H A D | register_pressure.cpp | 217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
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| /third_party/spirv-tools/source/opt/ |
| H A D | register_pressure.cpp | 216 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
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| /third_party/backends/backend/ |
| H A D | rts8891_low.h | 220 SANE_Int reg_count; member
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| /third_party/mesa3d/src/freedreno/ir3/ |
| H A D | ir3.c | 256 ir3_get_reg_dependent_max_waves(const struct ir3_compiler *compiler, unsigned reg_count, bool double_threadsize) ir3_get_reg_dependent_max_waves() argument
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| H A D | ir3_ra.c | 2326 unsigned reg_count = DIV_ROUND_UP(pressure, 2 * 4); in calc_target_full_pressure() local
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| /third_party/mesa3d/src/util/ |
| H A D | register_allocate.c | 429 unsigned int reg_count = blob_read_uint32(blob); in ra_set_deserialize() local
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| /third_party/node/deps/v8/src/compiler/ |
| H A D | bytecode-analysis.cc | 119 uint32_t reg_count = iterator.GetRegisterCountOperand(i + 1); in UpdateInLivenessForOutOperand() local
177 uint32_t reg_count = iterator.GetRegisterCountOperand(i + 1); in UpdateInLivenessForInOperand() local
438 uint32_t reg_count = iterator.GetRegisterCountOperand(i); in UpdateAssignments() local
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| H A D | bytecode-graph-builder.cc | 2447 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); in BuildCallVarArgs() local
2546 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); in VisitCallWithSpread() local
2579 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); in VisitCallJSRuntime() local
2590 ProcessCallRuntimeArguments( const Operator* call_runtime_op, interpreter::Register receiver, size_t reg_count) ProcessCallRuntimeArguments() argument
2610 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitCallRuntime() local
2638 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitCallRuntimeForPair() local
2681 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitConstruct() local
2713 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitConstructWithSpread() local
2746 size_t reg_count = bytecode_iterator().GetRegisterCountOperand(2); VisitInvokeIntrinsic() local
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| H A D | ir2_private.h | 179 unsigned reg_count; member
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | register-arm64.h | 331 int reg_count = IsVectorFormat(format) ? LaneCountFromFormat(format) : 1; in Create() local
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| /third_party/node/deps/v8/src/maglev/ |
| H A D | maglev-graph-builder.cc | 643 int reg_count = argc_count_with_recv; in BuildCallFromRegisters() local
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| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.cc | 489 PopulateRegisterArray(Register* w, Register* x, Register* r, int reg_size, int reg_count, RegList allowed) PopulateRegisterArray() argument
520 PopulateVRegisterArray(VRegister* s, VRegister* d, VRegister* v, int reg_size, int reg_count, RegList allowed) PopulateVRegisterArray() argument
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 1072 void SetRegCount(int reg_count) { in SetRegCount() argument
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| H A D | disasm-aarch64.cc | 6749 int reg_count = instr->ExtractBits(22, 21) + 1; in Disassembler() local
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| H A D | simulator-aarch64.cc | 1540 PrintVRegistersForStructuredAccess(int rt_code, int reg_count, uint16_t focus_mask, PrintRegisterFormat format) Simulator() argument
1559 PrintZRegistersForStructuredAccess(int rt_code, int q_index, int reg_count, uint16_t focus_mask, PrintRegisterFormat format) Simulator() argument
1851 PrintVStructAccess(int rt_code, int reg_count, PrintRegisterFormat format, const char* op, uintptr_t address) Simulator() argument
1881 PrintVSingleStructAccess(int rt_code, int reg_count, int lane, PrintRegisterFormat format, const char* op, uintptr_t address) Simulator() argument
1900 PrintVReplicatingStructAccess(int rt_code, int reg_count, PrintRegisterFormat format, const char* op, uintptr_t address) Simulator() argument
1943 PrintZStructAccess(int rt_code, int reg_count, const LogicPRegister& pg, PrintRegisterFormat format, int msize_in_bytes, const char* op, const LogicSVEAddressVector& addr) Simulator() argument
8235 int reg_count = 1; Simulator() local
8506 int reg_count = 0; Simulator() local
12537 int reg_count = instr->ExtractBits(22, 21) + 1; Simulator() local
12973 int reg_count = instr->ExtractBits(22, 21) + 1; Simulator() local
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_cmd_buffer.c | 2429 unsigned reg_offset = 0, reg_count = 0; in radv_load_ds_clear_metadata() local
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