Lines Matching refs:core
177 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) {
181 int64_t result_x = core->xreg(reg.GetCode());
188 uint32_t result_w = core->wreg(reg.GetCode());
189 return Equal32(expected, core, result_w);
194 const RegisterDump* core,
198 uint64_t result = core->xreg(reg.GetCode());
199 return Equal64(reference, core, result, option);
204 const RegisterDump* core,
207 uint64_t result = core->xreg(reg.GetCode());
208 return NotEqual64(reference, core, result);
214 const RegisterDump* core,
220 QRegisterValue result = core->qreg(vreg.GetCode());
221 return Equal128(expected, core, result);
226 const RegisterDump* core,
231 uint64_t result_64 = core->dreg_bits(fpreg.GetCode());
239 return EqualFP16(expected, core, core->hreg(fpreg.GetCode()));
244 const RegisterDump* core,
249 uint64_t result_64 = core->dreg_bits(fpreg.GetCode());
258 return EqualFP32(expected, core, core->sreg(fpreg.GetCode()));
263 const RegisterDump* core,
266 return EqualFP64(expected, core, core->dreg(fpreg.GetCode()));
271 const RegisterDump* core,
275 int64_t reference = core->xreg(reg0.GetCode());
276 int64_t result = core->xreg(reg1.GetCode());
277 return Equal64(reference, core, result, option);
282 const RegisterDump* core,
285 int64_t expected = core->xreg(reg0.GetCode());
286 int64_t result = core->xreg(reg1.GetCode());
287 return NotEqual64(expected, core, result);
292 const RegisterDump* core,
295 uint64_t result = core->dreg_bits(vreg.GetCode());
296 return Equal64(expected, core, result);
359 const RegisterDump* core,
365 // the check. For example, in `EqualSVELane(-1, core, z0.VnB())`, the expected
371 uint64_t result = core->zreg_lane(reg.GetCode(), lane_size, lane);
388 const RegisterDump* core,
397 uint64_t result = core->preg_lane(reg.GetCode(), p_bits_per_lane, lane);
679 // Dump core registers.