Lines Matching defs:reg
177 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) {
178 VIXL_ASSERT(reg.Is32Bits());
181 int64_t result_x = core->xreg(reg.GetCode());
188 uint32_t result_w = core->wreg(reg.GetCode());
195 const Register& reg,
197 VIXL_ASSERT(reg.Is64Bits());
198 uint64_t result = core->xreg(reg.GetCode());
205 const Register& reg) {
206 VIXL_ASSERT(reg.Is64Bits());
207 uint64_t result = core->xreg(reg.GetCode());
360 const ZRegister& reg,
362 unsigned lane_size = reg.GetLaneSizeInBits();
371 uint64_t result = core->zreg_lane(reg.GetCode(), lane_size, lane);
374 std::string reg_name = reg.GetArchitecturalName();
389 const PRegister& reg,
391 VIXL_ASSERT(reg.HasLaneSize());
392 VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0);
393 unsigned p_bits_per_lane = reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit;
397 uint64_t result = core->preg_lane(reg.GetCode(), p_bits_per_lane, lane);
400 std::string reg_name = reg.GetArchitecturalName();
615 T reg(i);
616 __ Str(reg, SVEMemOperand(dump));
617 __ Add(dump, dump, reg.GetMaxSizeInBytes());
630 T reg(i, reg_size_in_bytes * kBitsPerByte);
631 __ Str(reg, MemOperand(dump));
720 CPURegister reg = scratch_registers.PopLowestIndex();
721 Register x = reg.X();
722 Register w = reg.W();
723 unsigned code = reg.GetCode();