Lines Matching defs:expected
58 bool Equal32(uint32_t expected, const RegisterDump*, uint32_t result) {
59 if (result != expected) {
61 expected,
65 return expected == result;
92 bool Equal128(QRegisterValue expected,
95 if (!expected.Equals(result)) {
99 expected.GetLane<uint64_t>(1),
100 expected.GetLane<uint64_t>(0),
105 return expected.Equals(result);
109 bool EqualFP16(Float16 expected, const RegisterDump*, Float16 result) {
110 uint16_t e_rawbits = Float16ToRawbits(expected);
115 if (IsNaN(expected) || IsZero(expected)) {
123 FPToFloat(expected, kIgnoreDefaultNaN),
133 bool EqualFP32(float expected, const RegisterDump*, float result) {
134 if (FloatToRawbits(expected) == FloatToRawbits(result)) {
137 if (IsNaN(expected) || (expected == 0.0)) {
139 FloatToRawbits(expected),
145 expected,
146 FloatToRawbits(expected),
155 bool EqualFP64(double expected, const RegisterDump*, double result) {
156 if (DoubleToRawbits(expected) == DoubleToRawbits(result)) {
160 if (IsNaN(expected) || (expected == 0.0)) {
162 DoubleToRawbits(expected),
168 expected,
169 DoubleToRawbits(expected),
177 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) {
184 expected,
189 return Equal32(expected, core, result_w);
217 QRegisterValue expected;
218 expected.SetLane(0, expected_l);
219 expected.SetLane(1, expected_h);
221 return Equal128(expected, core, result);
225 bool EqualFP16(Float16 expected,
234 Float16ToRawbits(expected),
235 FPToFloat(expected, kIgnoreDefaultNaN),
239 return EqualFP16(expected, core, core->hreg(fpreg.GetCode()));
243 bool EqualFP32(float expected,
252 FloatToRawbits(expected),
253 expected,
258 return EqualFP32(expected, core, core->sreg(fpreg.GetCode()));
262 bool EqualFP64(double expected,
266 return EqualFP64(expected, core, core->dreg(fpreg.GetCode()));
285 int64_t expected = core->xreg(reg0.GetCode());
287 return NotEqual64(expected, core, result);
291 bool Equal64(uint64_t expected,
296 return Equal64(expected, core, result);
312 bool EqualNzcv(uint32_t expected, uint32_t result) {
313 VIXL_ASSERT((expected & ~NZCVFlag) == 0);
315 if (result != expected) {
317 FlagN(expected),
318 FlagZ(expected),
319 FlagC(expected),
320 FlagV(expected),
358 bool EqualSVELane(uint64_t expected,
364 // `expected`, but truncate them to an appropriately-sized unsigned value for
365 // the check. For example, in `EqualSVELane(-1, core, z0.VnB())`, the expected
367 VIXL_ASSERT(IsUintN(lane_size, expected) ||
368 IsIntN(lane_size, RawbitsToInt64(expected)));
369 expected &= GetUintMask(lane_size);
372 if (expected != result) {
379 expected,
387 bool EqualSVELane(uint64_t expected,
394 VIXL_ASSERT(IsUintN(p_bits_per_lane, expected));
395 expected &= GetUintMask(p_bits_per_lane);
398 if (expected != result) {
405 expected,
417 RawChunk expected;
420 bool IsEqual() const { return expected == result; }
423 bool EqualMemory(const void* expected,
427 if (memcmp(expected, result, size_in_bytes) == 0) return true;
440 const char* expected_it = reinterpret_cast<const char*>(expected);
452 memcpy(&chunk.expected, expected_it, kChunkSize);
478 context.front().expected,