Lines Matching refs:base
392 * necessary prior to changing the surface state base address. We've
394 * command buffers which clear depth, reset state base address, and then
420 /* After re-setting the surface state base address, we have to do some
700 /* We program most base addresses once at context initialization time.
701 * Each base address points at a 4GB memory zone, and never needs to
887 struct pipe_screen *pscreen = &batch->screen->base;
2266 if (tex && tex->res->base.b.target == PIPE_TEXTURE_3D)
2357 * and base data type for elements, as specified in Table X.1. The
2542 /* initialize base object */
2543 isv->base = *tmpl;
2544 isv->base.context = ctx;
2545 isv->base.texture = NULL;
2546 pipe_reference_init(&isv->base.reference, 1);
2547 pipe_resource_reference(&isv->base.texture, tex);
2556 tex = util_format_has_depth(desc) ? &zres->base.b : &sres->base.b;
2563 if (isv->base.target == PIPE_TEXTURE_CUBE ||
2564 isv->base.target == PIPE_TEXTURE_CUBE_ARRAY)
2629 return &isv->base;
2770 struct pipe_surface *psurf = &surf->base;
2876 util_copy_image_view(&iv->base, img);
2894 if (res->base.b.target != PIPE_BUFFER) {
2921 util_range_add(&res->base.b, &res->valid_buffer_range, img->u.buf.offset,
2935 pipe_resource_reference(&iv->base.resource, NULL);
2961 return view && view->res->base.b.target == PIPE_TEXTURE_3D;
3047 assert(res->base.b.target == PIPE_BUFFER);
3048 util_range_add(&res->base.b, &res->valid_buffer_range,
3049 0, res->base.b.width0);
3552 pipe_resource_reference(&ssbo->buffer, &res->base.b);
3566 util_range_add(&res->base.b, &res->valid_buffer_range, ssbo->buffer_offset,
3642 vb.BufferSize = res->base.b.width0 - (int) buffer->buffer_offset;
3832 pipe_reference_init(&cso->base.reference, 1);
3833 pipe_resource_reference(&cso->base.buffer, p_res);
3834 cso->base.buffer_offset = buffer_offset;
3835 cso->base.buffer_size = buffer_size;
3836 cso->base.context = ctx;
3838 util_range_add(&res->base.b, &res->valid_buffer_range, buffer_offset,
3841 return &cso->base;
3850 pipe_resource_reference(&cso->base.buffer, NULL);
3892 iris_dirty_for_history(ice, (void *)tgt->base.buffer);
3928 struct iris_resource *res = (void *) tgt->base.buffer;
3957 rw_bo(NULL, res->bo->address + tgt->base.buffer_offset,
3964 sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
5056 struct iris_resource *res = (void *) iv->base.resource;
5061 bool write = iv->base.shader_access & PIPE_IMAGE_ACCESS_WRITE;
5069 iris_image_view_aux_usage(ice, &iv->base, info);
5323 iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer),
5523 * if you don't set the "Address Modify Enable" bit for the base.
6259 iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer),
7057 mi_iadd_imm(&b, mi_mem32(addr), -so->base.buffer_offset);
7252 cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
7432 pipe_resource_reference(&shs->image[i].base.resource, NULL);
7471 assert(res->base.b.target == PIPE_BUFFER);
7566 .buffer = &res->base.b,
7595 struct iris_bo *bo = iris_resource_bo(iv->base.resource);