Lines Matching defs:view

2466                    struct isl_view *view,
2474 .view = view,
2475 .mocs = iris_mocs(res->bo, isl_dev, view->usage),
2509 struct isl_view *view,
2520 fill_surface_state(isl_dev, map, res, surf, view, aux_usage,
2572 isv->view = (struct isl_view) {
2588 !isl_format_supports_ccs_e(devinfo, isv->view.format)) {
2601 /* Fill out SURFACE_STATE for this view. */
2603 isv->view.base_level = tmpl->u.tex.first_level;
2604 isv->view.levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1;
2607 isv->view.base_array_layer = 0;
2608 isv->view.array_len = 1;
2614 isv->view.base_array_layer = tmpl->u.tex.first_layer;
2615 isv->view.array_len =
2620 &isv->res->surf, &isv->view, 0, 0, 0);
2624 isv->view.format, isv->view.swizzle,
2646 * In Gallium nomenclature, "surfaces" are a view of a resource that
2685 struct isl_view *view = &surf->view;
2686 *view = (struct isl_view) {
2747 * have a renderable view format. We must be attempting to upload
2748 * blocks of compressed data via an uncompressed view.
2752 * and create an uncompressed view with multiple layers, however.
2756 assert(view->levels == 1);
2759 &res->surf, view,
2760 &isl_surf, view, &offset_B,
2794 !isl_format_supports_ccs_e(devinfo, view->format)) {
2804 &isl_surf, view, offset_B, tile_x_el, tile_y_el);
2895 struct isl_view view = {
2914 &res->surf, &view, 0, 0, 0);
2919 &res->surf, &view);
2959 is_sampler_view_3d(const struct iris_sampler_view *view)
2961 return view && view->res->base.b.target == PIPE_TEXTURE_3D;
2987 struct iris_sampler_view *view = (void *) pview;
2991 is_sampler_view_3d(view))
3003 if (view) {
3004 view->res->bind_history |= PIPE_BIND_SAMPLER_VIEW;
3005 view->res->bind_stages |= 1 << stage;
3010 &view->surface_state, view->res->bo);
3283 struct isl_view view = {
3292 .view = &view,
3300 view.base_level = cso->zsbuf->u.tex.level;
3301 view.base_array_layer = cso->zsbuf->u.tex.first_layer;
3302 view.array_len =
3306 view.usage |= ISL_SURF_USAGE_DEPTH_BIT;
3310 info.mocs = iris_mocs(zres->bo, isl_dev, view.usage);
3312 view.format = zres->surf.format;
3314 if (iris_resource_level_has_hiz(zres, view.base_level)) {
3324 view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
3329 view.format = stencil_res->surf.format;
3330 info.mocs = iris_mocs(stencil_res->bo, isl_dev, view.usage);
4908 struct isl_view *view)
4929 fill_surface_states(isl_dev, surf_state, res, &res->surf, view, 0, 0, 0);
4977 update_clear_value(ice, batch, res, &surf->surface_state, &surf->view);
5006 iris_resource_texture_aux_usage(ice, isv->res, isv->view.format);
5014 &isv->view);
5167 struct iris_sampler_view *view = shs->textures[i];
5168 uint32_t addr = view ? use_sampler_view(ice, batch, view)