Lines Matching defs:state
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
38 * OpenGL involves frequently mutating context state, which is mirrored in
42 * than inventing new state all the time, applications usually mutate to swap
45 * Gallium isolates us from this mutation by tracking API state, and
47 * complex, or typically reusable state can be created once, then reused
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
68 * create/bind/track state. The second are the draw-time upload functions,
70 * the context state and emit the commands into the actual batch.
310 * Allocate space for some indirect state.
312 * Return a pointer to the map (to fill it out) and a state ref (for
313 * referring to the state in GPU commands).
327 * Stream out temporary/short-lived state.
330 * returned offset (which works because all state lives in 32-bit memory
392 * necessary prior to changing the surface state base address. We've
394 * command buffers which clear depth, reset state base address, and then
420 /* After re-setting the surface state base address, we have to do some
425 * Coherency with system memory in the state cache, like the texture
434 * Surface_State_Base_Addr are altered, the L1 state cache must be
435 * invalidated to ensure the new surface or sampler state is fetched
443 * This bit controls the invalidation of the L1 and L2 state caches
446 * Unfortunately, experimentation seems to indicate that state cache
448 * regards to surface state and binding tables. In stead, it seems that
822 stream_state(batch, ice->state.dynamic_uploader, &tmp,
901 pipe_resource_reference(&ice->state.pixel_hashing_tables, NULL);
902 ice->state.pixel_hashing_tables = pscreen->resource_create(pscreen, &tmpl);
904 struct iris_resource *res = (struct iris_resource *)ice->state.pixel_hashing_tables;
906 uint32_t *map = pipe_buffer_map_range(&ice->ctx, ice->state.pixel_hashing_tables,
1016 * Upload initial GPU state for any kind of context.
1054 * Upload the initial GPU state for a render context.
1056 * This sets some invariant state that needs to be programmed a particular
1233 uint32_t state[GENX(VERTEX_BUFFER_STATE_length)];
1258 * Generation-specific context state (ice->state.genx->...).
1260 * Most state can go in iris_context directly, but these encode hardware
1298 const struct pipe_blend_color *state)
1303 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
1304 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
1308 * Gallium CSO for blend state (see pipe_blend_state).
1351 const struct pipe_blend_state *state)
1360 cso->alpha_to_coverage = state->alpha_to_coverage;
1366 &state->rt[state->independent_blend_enable ? i : 0];
1369 fix_blendfactor(rt->rgb_src_factor, state->alpha_to_one);
1371 fix_blendfactor(rt->alpha_src_factor, state->alpha_to_one);
1373 fix_blendfactor(rt->rgb_dst_factor, state->alpha_to_one);
1375 fix_blendfactor(rt->alpha_dst_factor, state->alpha_to_one);
1388 be.LogicOpEnable = state->logicop_enable;
1389 be.LogicOpFunction = state->logicop_func;
1423 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
1428 (int) fix_blendfactor(state->rt[0].rgb_src_factor, state->alpha_to_one);
1430 (int) fix_blendfactor(state->rt[0].alpha_src_factor, state->alpha_to_one);
1432 (int) fix_blendfactor(state->rt[0].rgb_dst_factor, state->alpha_to_one);
1434 (int) fix_blendfactor(state->rt[0].alpha_dst_factor, state->alpha_to_one);
1438 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
1440 bs.AlphaToOneEnable = state->alpha_to_one;
1441 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
1442 bs.ColorDitherEnable = state->dither;
1446 cso->dual_color_blending = util_blend_state_is_dual(state, 0);
1457 iris_bind_blend_state(struct pipe_context *ctx, void *state)
1460 struct iris_blend_state *cso = state;
1462 ice->state.cso_blend = cso;
1464 ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
1465 ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
1466 ice->state.stage_dirty |= ice->state.stage_dirty_for_nos[IRIS_NOS_BLEND];
1469 ice->state.dirty |= IRIS_DIRTY_PMA_FIX;
1492 * Gallium CSO for depth, stencil, and alpha testing state.
1519 * testing state since we need pieces of it in a variety of places.
1523 const struct pipe_depth_stencil_alpha_state *state)
1528 bool two_sided_stencil = state->stencil[1].enabled;
1530 cso->alpha_enabled = state->alpha_enabled;
1531 cso->alpha_func = state->alpha_func;
1532 cso->alpha_ref_value = state->alpha_ref_value;
1533 cso->depth_writes_enabled = state->depth_writemask;
1534 cso->depth_test_enabled = state->depth_enabled;
1536 state->stencil[0].writemask != 0 ||
1537 (two_sided_stencil && state->stencil[1].writemask != 0);
1540 assert(!(state->depth_func == PIPE_FUNC_EQUAL && state->depth_writemask));
1543 wmds.StencilFailOp = state->stencil[0].fail_op;
1544 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
1545 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
1547 translate_compare_func(state->stencil[0].func);
1548 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
1549 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
1550 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
1552 translate_compare_func(state->stencil[1].func);
1553 wmds.DepthTestFunction = translate_compare_func(state->depth_func);
1555 wmds.StencilTestEnable = state->stencil[0].enabled;
1557 state->stencil[0].writemask != 0 ||
1558 (two_sided_stencil && state->stencil[1].writemask != 0);
1559 wmds.DepthTestEnable = state->depth_enabled;
1560 wmds.DepthBufferWriteEnable = state->depth_writemask;
1561 wmds.StencilTestMask = state->stencil[0].valuemask;
1562 wmds.StencilWriteMask = state->stencil[0].writemask;
1563 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
1564 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
1575 depth_bounds.DepthBoundsTestEnable = state->depth_bounds_test;
1576 depth_bounds.DepthBoundsTestMinValue = state->depth_bounds_min;
1577 depth_bounds.DepthBoundsTestMaxValue = state->depth_bounds_max;
1590 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
1593 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
1594 struct iris_depth_stencil_alpha_state *new_cso = state;
1598 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
1601 ice->state.dirty |= IRIS_DIRTY_PS_BLEND | IRIS_DIRTY_BLEND_STATE;
1604 ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
1607 ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
1609 ice->state.depth_writes_enabled = new_cso->depth_writes_enabled;
1610 ice->state.stencil_writes_enabled = new_cso->stencil_writes_enabled;
1614 ice->state.dirty |= IRIS_DIRTY_DEPTH_BOUNDS;
1618 ice->state.cso_zsa = new_cso;
1619 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
1620 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
1621 ice->state.stage_dirty |=
1622 ice->state.stage_dirty_for_nos[IRIS_NOS_DEPTH_STENCIL_ALPHA];
1625 ice->state.dirty |= IRIS_DIRTY_PMA_FIX;
1636 const struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1637 const struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
1638 const struct iris_blend_state *cso_blend = ice->state.cso_blend;
1640 /* In very specific combinations of state, we can instruct Gfx8-9 hardware
1641 * to avoid stalling at the pixel mask array. The state equations are
1757 struct iris_genx_state *genx = ice->state.genx;
1799 * Gallium CSO for rasterizer state.
1812 bool flatshade; /* for shader state */
1814 bool clamp_fragment_color; /* for shader state */
1815 bool light_twoside; /* for shader state */
1831 get_line_width(const struct pipe_rasterizer_state *state)
1833 float line_width = state->line_width;
1841 if (!state->multisample && !state->line_smooth)
1842 line_width = roundf(state->line_width);
1844 if (!state->multisample && state->line_smooth && line_width < 1.5f) {
1865 const struct pipe_rasterizer_state *state)
1870 cso->multisample = state->multisample;
1871 cso->force_persample_interp = state->force_persample_interp;
1872 cso->clip_halfz = state->clip_halfz;
1873 cso->depth_clip_near = state->depth_clip_near;
1874 cso->depth_clip_far = state->depth_clip_far;
1875 cso->flatshade = state->flatshade;
1876 cso->flatshade_first = state->flatshade_first;
1877 cso->clamp_fragment_color = state->clamp_fragment_color;
1878 cso->light_twoside = state->light_twoside;
1879 cso->rasterizer_discard = state->rasterizer_discard;
1880 cso->half_pixel_center = state->half_pixel_center;
1881 cso->sprite_coord_mode = state->sprite_coord_mode;
1882 cso->sprite_coord_enable = state->sprite_coord_enable;
1883 cso->line_stipple_enable = state->line_stipple_enable;
1884 cso->poly_stipple_enable = state->poly_stipple_enable;
1886 state->conservative_raster_mode == PIPE_CONSERVATIVE_RASTER_POST_SNAP;
1889 state->fill_front == PIPE_POLYGON_MODE_POINT ||
1890 state->fill_back == PIPE_POLYGON_MODE_POINT;
1892 state->fill_front == PIPE_POLYGON_MODE_LINE ||
1893 state->fill_back == PIPE_POLYGON_MODE_LINE;
1898 if (state->clip_plane_enable != 0)
1899 cso->num_clip_plane_consts = util_logbase2(state->clip_plane_enable) + 1;
1903 float line_width = get_line_width(state);
1909 state->line_smooth ? _10pixels : _05pixels;
1910 sf.LastPixelEnable = state->line_last_pixel;
1912 sf.SmoothPointEnable = (state->point_smooth || state->multisample) &&
1913 !state->point_quad_rasterization;
1914 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
1915 sf.PointWidth = CLAMP(state->point_size, 0.125f, 255.875f);
1917 if (state->flatshade_first) {
1927 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
1928 rr.CullMode = translate_cull_mode(state->cull_face);
1929 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
1930 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
1931 rr.DXMultisampleRasterizationEnable = state->multisample;
1932 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
1933 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
1934 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
1935 rr.GlobalDepthOffsetConstant = state->offset_units * 2;
1936 rr.GlobalDepthOffsetScale = state->offset_scale;
1937 rr.GlobalDepthOffsetClamp = state->offset_clamp;
1938 rr.SmoothPointEnable = state->point_smooth;
1939 rr.AntialiasingEnable = state->line_smooth;
1940 rr.ScissorRectangleEnable = state->scissor;
1942 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
1943 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
1947 rr.ViewportZClipTestEnable = (state->depth_clip_near || state->depth_clip_far);
1956 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
1958 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
1964 if (state->flatshade_first) {
1980 wm.LineStippleEnable = state->line_stipple_enable;
1981 wm.PolygonStippleEnable = state->poly_stipple_enable;
1985 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
1988 if (state->line_stipple_enable) {
1989 line.LineStipplePattern = state->line_stipple_pattern;
2004 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
2007 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
2008 struct iris_rasterizer_state *new_cso = state;
2013 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
2016 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
2019 ice->state.dirty |= IRIS_DIRTY_WM;
2022 ice->state.dirty |= IRIS_DIRTY_STREAMOUT | IRIS_DIRTY_CLIP;
2025 ice->state.dirty |= IRIS_DIRTY_STREAMOUT;
2029 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
2034 ice->state.dirty |= IRIS_DIRTY_SBE;
2037 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_FS;
2040 ice->state.cso_rast = new_cso;
2041 ice->state.dirty |= IRIS_DIRTY_RASTER;
2042 ice->state.dirty |= IRIS_DIRTY_CLIP;
2043 ice->state.stage_dirty |=
2044 ice->state.stage_dirty_for_nos[IRIS_NOS_RASTERIZER];
2059 * Gallium CSO for sampler state.
2068 /* Sampler state structure to use for 3D textures in order to
2077 const struct pipe_sampler_state *state,
2080 float min_lod = state->min_lod;
2081 unsigned mag_img_filter = state->mag_img_filter;
2084 if (state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE &&
2085 state->min_lod > 0.0f) {
2087 mag_img_filter = state->min_img_filter;
2091 samp.TCXAddressControlMode = translate_wrap(state->wrap_s);
2092 samp.TCYAddressControlMode = translate_wrap(state->wrap_t);
2093 samp.TCZAddressControlMode = translate_wrap(state->wrap_r);
2094 samp.CubeSurfaceControlMode = state->seamless_cube_map;
2095 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
2096 samp.MinModeFilter = state->min_img_filter;
2098 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
2102 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
2107 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
2115 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
2121 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
2127 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
2128 samp.ShadowFunction = translate_shadow_func(state->compare_func);
2134 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
2135 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
2151 const struct pipe_sampler_state *state)
2163 unsigned wrap_s = translate_wrap(state->wrap_s);
2164 unsigned wrap_t = translate_wrap(state->wrap_t);
2165 unsigned wrap_r = translate_wrap(state->wrap_r);
2167 memcpy(&cso->border_color, &state->border_color, sizeof(cso->border_color));
2173 fill_sampler_state(cso->sampler_state, state, state->max_anisotropy);
2176 /* Fill an extra sampler state structure with anisotropic filtering
2179 fill_sampler_state(cso->sampler_state_3d, state, 0);
2196 struct iris_shader_state *shs = &ice->state.shaders[stage];
2203 struct iris_sampler_state *state = states ? states[i] : NULL;
2204 if (shs->samplers[start + i] != state) {
2205 shs->samplers[start + i] = state;
2211 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_SAMPLER_STATES_VS << stage;
2218 * Also fill out the border color state pointers.
2224 struct iris_shader_state *shs = &ice->state.shaders[stage];
2238 * in the dynamic state memory zone, so we can point to it via the
2243 upload_state(ice->state.dynamic_uploader, &shs->sampler_table, size, 32);
2250 iris_record_state_size(ice->state.sizes,
2255 ice->state.need_border_colors &= ~(1 << stage);
2258 struct iris_sampler_state *state = shs->samplers[i];
2261 if (!state) {
2264 const uint32_t *sampler_state = state->sampler_state;
2267 sampler_state = state->sampler_state_3d;
2270 if (!state->needs_border_color) {
2273 ice->state.need_border_colors |= 1 << stage;
2281 union pipe_color_union *color = &state->border_color;
2634 struct pipe_sampler_view *state)
2636 struct iris_sampler_view *isv = (void *) state;
2637 pipe_resource_reference(&state->texture, NULL);
2712 /* The minimum array element field of the surface state structure is
2860 struct iris_shader_state *shs = &ice->state.shaders[stage];
2862 struct iris_genx_state *genx = ice->state.genx;
2933 upload_surface_states(ice->state.surface_uploader, &iv->surface_state);
2941 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_VS << stage;
2942 ice->state.dirty |=
2948 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS << stage;
2979 struct iris_shader_state *shs = &ice->state.shaders[stage];
2992 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_SAMPLER_STATES_VS << stage;
3009 update_surface_state_addrs(ice->state.surface_uploader,
3018 ice->state.stage_dirty |= (IRIS_STAGE_DIRTY_BINDINGS_VS << stage);
3019 ice->state.dirty |=
3043 pipe_resource_reference(&ice->state.global_bindings[start_slot + i],
3056 pipe_resource_reference(&ice->state.global_bindings[start_slot + i],
3061 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_CS;
3073 struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_TESS_CTRL];
3075 memcpy(&ice->state.default_outer_level[0], &default_outer_level[0], 4 * sizeof(float));
3076 memcpy(&ice->state.default_inner_level[0], &default_inner_level[0], 2 * sizeof(float));
3078 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TCS;
3087 ice->state.patch_vertices = patch_vertices;
3104 const struct pipe_clip_state *state)
3107 struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_VERTEX];
3108 struct iris_shader_state *gshs = &ice->state.shaders[MESA_SHADER_GEOMETRY];
3109 struct iris_shader_state *tshs = &ice->state.shaders[MESA_SHADER_TESS_EVAL];
3111 memcpy(&ice->state.clip_planes, state, sizeof(*state));
3113 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS |
3126 const struct pipe_poly_stipple *state)
3129 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
3130 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
3144 ice->state.sample_mask = sample_mask & 0xffff;
3145 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
3151 * This corresponds to our SCISSOR_RECT state structures. It's an
3170 ice->state.scissors[start_slot + i] = (struct pipe_scissor_state) {
3174 ice->state.scissors[start_slot + i] = (struct pipe_scissor_state) {
3181 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
3191 const struct pipe_stencil_ref state)
3194 memcpy(&ice->state.stencil_ref, &state, sizeof(state));
3196 ice->state.dirty |= IRIS_DIRTY_STENCIL_REF;
3198 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
3200 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
3204 viewport_extent(const struct pipe_viewport_state *state, int axis, float sign)
3206 return copysignf(state->scale[axis], sign) + state->translate[axis];
3224 memcpy(&ice->state.viewports[start_slot], states, sizeof(*states) * count);
3226 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
3228 if (ice->state.cso_rast && (!ice->state.cso_rast->depth_clip_near ||
3229 !ice->state.cso_rast->depth_clip_far))
3230 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
3241 const struct pipe_framebuffer_state *state)
3246 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
3250 unsigned samples = util_framebuffer_get_num_samples(state);
3251 unsigned layers = util_framebuffer_get_num_layers(state);
3254 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
3258 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_FS;
3261 if (cso->nr_cbufs != state->nr_cbufs) {
3262 ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
3266 ice->state.dirty |= IRIS_DIRTY_CLIP;
3269 if (cso->width != state->width || cso->height != state->height) {
3270 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
3273 if (cso->zsbuf || state->zsbuf) {
3274 ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
3277 util_copy_framebuffer_state(cso, state);
3281 struct iris_depth_buffer_state *cso_z = &ice->state.genx->depth_buffer;
3320 ice->state.hiz_usage = info.hiz_usage;
3339 upload_state(ice->state.surface_uploader, &ice->state.null_fb,
3345 ice->state.null_fb.offset +=
3346 iris_bo_offset_from_base_address(iris_resource_bo(ice->state.null_fb.res));
3349 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_FS;
3351 ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
3353 ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
3355 ice->state.stage_dirty |=
3356 ice->state.stage_dirty_for_nos[IRIS_NOS_FRAMEBUFFER];
3359 ice->state.dirty |= IRIS_DIRTY_PMA_FIX;
3376 struct iris_shader_state *shs = &ice->state.shaders[stage];
3401 ice->state.dirty |= (IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES |
3428 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS << stage;
3436 UNUSED struct iris_genx_state *genx = ice->state.genx;
3437 struct iris_shader_state *shs = &ice->state.shaders[stage];
3481 value = fui(ice->state.clip_planes.ucp[plane][comp]);
3484 value = ice->state.vertices_per_patch;
3492 value = ice->state.vertices_per_patch;
3497 value = fui(ice->state.default_outer_level[i]);
3499 value = fui(ice->state.default_inner_level[0]);
3501 value = fui(ice->state.default_inner_level[1]);
3505 value = ice->state.last_block[i];
3538 struct iris_shader_state *shs = &ice->state.shaders[stage];
3575 ice->state.dirty |= (IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES |
3577 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_VS << stage;
3581 iris_delete_state(struct pipe_context *ctx, void *state)
3583 free(state);
3600 struct iris_genx_state *genx = ice->state.genx;
3602 ice->state.bound_vertex_buffers &=
3607 struct iris_vertex_buffer_state *state =
3611 pipe_resource_reference(&state->resource, NULL);
3619 state->resource != buffer->buffer.resource)
3620 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFER_FLUSHES;
3623 pipe_resource_reference(&state->resource, NULL);
3624 state->resource = buffer->buffer.resource;
3626 pipe_resource_reference(&state->resource, buffer->buffer.resource);
3628 struct iris_resource *res = (void *) state->resource;
3630 state->offset = (int) buffer->buffer_offset;
3633 ice->state.bound_vertex_buffers |= 1ull << (start_slot + i);
3637 iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) {
3659 struct iris_vertex_buffer_state *state =
3662 pipe_resource_reference(&state->resource, NULL);
3665 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
3693 const struct pipe_vertex_element *state)
3726 iris_format_for_usage(devinfo, state[i].src_format, 0);
3741 ve.VertexBufferIndex = state[i].vertex_buffer_index;
3743 ve.SourceElementOffset = state[i].src_offset;
3753 vi.InstancingEnable = state[i].instance_divisor > 0;
3754 vi.InstanceDataStepRate = state[i].instance_divisor;
3767 iris_format_for_usage(devinfo, state[edgeflag_index].src_format, 0);
3770 ve.VertexBufferIndex = state[edgeflag_index].vertex_buffer_index;
3772 ve.SourceElementOffset = state[edgeflag_index].src_offset;
3783 vi.InstancingEnable = state[edgeflag_index].instance_divisor > 0;
3784 vi.InstanceDataStepRate = state[edgeflag_index].instance_divisor;
3795 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
3798 struct iris_vertex_element_state *old_cso = ice->state.cso_vertex_elements;
3799 struct iris_vertex_element_state *new_cso = state;
3805 ice->state.dirty |= IRIS_DIRTY_VF_SGVS;
3807 ice->state.cso_vertex_elements = state;
3808 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
3846 struct pipe_stream_output_target *state)
3848 struct iris_stream_output_target *cso = (void *) state;
3870 struct iris_genx_state *genx = ice->state.genx;
3875 if (ice->state.streamout_active != active) {
3876 ice->state.streamout_active = active;
3877 ice->state.dirty |= IRIS_DIRTY_STREAMOUT;
3885 ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST;
3889 (void *) ice->state.so_target[i];
3898 pipe_so_target_reference(&ice->state.so_target[i],
3909 struct iris_stream_output_target *tgt = (void *) ice->state.so_target[i];
3972 ice->state.dirty |= IRIS_DIRTY_SO_BUFFERS;
3981 * no dynamic state dependencies.
3984 * state-based settings. We capture the shader-related ones here, and merge
4180 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
4264 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
4279 return ice->state.prim_mode == PIPE_PRIM_POINTS;
4304 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
4357 * Populate VS program key fields based on the current state.
4365 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
4374 * Populate TCS program key fields based on the current state.
4383 * Populate TES program key fields based on the current state.
4391 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
4400 * Populate GS program key fields based on the current state.
4408 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
4417 * Populate FS program key fields based on the current state.
4425 const struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
4426 const struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
4427 const struct iris_rasterizer_state *rast = ice->state.cso_rast;
4428 const struct iris_blend_state *blend = ice->state.cso_blend;
4783 * Create any state packets corresponding to the given shader stage
4786 * get most of the state packet without having to reconstruct it.
4831 struct iris_bo *state_bo = iris_resource_bo(ice->state.unbound_tex.res);
4835 return ice->state.unbound_tex.offset;
4842 if (!ice->state.null_fb.res)
4845 struct iris_bo *state_bo = iris_resource_bo(ice->state.null_fb.res);
4849 return ice->state.null_fb.offset;
4897 "update fast clear: state cache invalidate",
4913 /* We only need to update the clear color in the surface state for gfx8 and
4914 * gfx9. Newer gens can read it directly from the clear color state buffer.
4917 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4931 upload_surface_states(ice->state.surface_uploader, surf_state);
4966 upload_surface_states(ice->state.surface_uploader,
4971 upload_surface_states(ice->state.surface_uploader,
5009 upload_surface_states(ice->state.surface_uploader, &isv->surface_state);
5096 const struct iris_binder *binder = &ice->state.binder;
5103 struct iris_shader_state *shs = &ice->state.shaders[stage];
5119 struct iris_state_ref *grid_data = &ice->state.grid_size;
5120 struct iris_state_ref *grid_state = &ice->state.grid_surf_state;
5129 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
5136 ice->state.draw_aux_usage[i], false,
5156 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
5160 false, ice->state.draw_aux_usage[i], true,
5274 * We don't need to re-emit all state every batch - the hardware context
5288 struct iris_genx_state *genx = ice->state.genx;
5290 const uint64_t clean = ~ice->state.dirty;
5291 const uint64_t stage_clean = ~ice->state.stage_dirty;
5294 iris_use_optional_res(batch, ice->state.last_res.cc_vp, false,
5299 iris_use_optional_res(batch, ice->state.last_res.sf_cl_vp, false,
5304 iris_use_optional_res(batch, ice->state.last_res.blend, false,
5309 iris_use_optional_res(batch, ice->state.last_res.color_calc, false,
5314 iris_use_optional_res(batch, ice->state.last_res.scissor, false,
5318 if (ice->state.streamout_active && (clean & IRIS_DIRTY_SO_BUFFERS)) {
5321 (void *) ice->state.so_target[i];
5335 struct iris_shader_state *shs = &ice->state.shaders[stage];
5373 struct iris_shader_state *shs = &ice->state.shaders[stage];
5395 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
5396 pin_depth_and_stencil_buffers(batch, cso_fb->zsbuf, ice->state.cso_zsa);
5399 iris_use_optional_res(batch, ice->state.last_res.index_buffer, false,
5403 uint64_t bound = ice->state.bound_vertex_buffers;
5413 iris_use_pinned_bo(batch, iris_resource_bo(ice->state.pixel_hashing_tables),
5416 assert(!ice->state.pixel_hashing_tables);
5425 const uint64_t stage_clean = ~ice->state.stage_dirty;
5428 struct iris_shader_state *shs = &ice->state.shaders[stage];
5444 iris_use_optional_res(batch, ice->state.last_res.cs_desc, false,
5457 iris_resource_bo(ice->state.last_res.cs_thread_ids);
5487 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
5577 /* If the aux-map state number increased, then we need to rewrite the
5617 struct iris_shader_state *shs = &ice->state.shaders[stage];
5758 switch (ice->state.genx->depth_reg_mode) {
5790 ice->state.genx->depth_reg_mode =
5804 const uint64_t dirty = ice->state.dirty;
5805 const uint64_t stage_dirty = ice->state.stage_dirty;
5811 struct iris_genx_state *genx = ice->state.genx;
5812 struct iris_binder *binder = &ice->state.binder;
5817 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
5822 stream_state(batch, ice->state.dynamic_uploader,
5823 &ice->state.last_res.cc_vp,
5824 4 * ice->state.num_viewports *
5826 for (int i = 0; i < ice->state.num_viewports; i++) {
5828 iris_viewport_zmin_zmax(&ice->state.viewports[i], cso_rast->clip_halfz,
5829 ice->state.window_space_position,
5850 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
5853 stream_state(batch, ice->state.dynamic_uploader,
5854 &ice->state.last_res.sf_cl_vp,
5855 4 * ice->state.num_viewports *
5858 for (unsigned i = 0; i < ice->state.num_viewports; i++) {
5859 const struct pipe_viewport_state *state = &ice->state.viewports[i];
5862 float vp_xmin = viewport_extent(state, 0, -1.0f);
5863 float vp_xmax = viewport_extent(state, 0, 1.0f);
5864 float vp_ymin = viewport_extent(state, 1, -1.0f);
5865 float vp_ymax = viewport_extent(state, 1, 1.0f);
5868 state->scale[0], state->scale[1],
5869 state->translate[0], state->translate[1],
5873 vp.ViewportMatrixElementm00 = state->scale[0];
5874 vp.ViewportMatrixElementm11 = state->scale[1];
5875 vp.ViewportMatrixElementm22 = state->scale[2];
5876 vp.ViewportMatrixElementm30 = state->translate[0];
5877 vp.ViewportMatrixElementm31 = state->translate[1];
5878 vp.ViewportMatrixElementm32 = state->translate[2];
5916 &ice->state.urb_deref_block_size,
5930 struct iris_blend_state *cso_blend = ice->state.cso_blend;
5931 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
5932 struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
5944 stream_state(batch, ice->state.dynamic_uploader,
5945 &ice->state.last_res.blend,
5964 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
5966 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
5970 stream_state(batch, ice->state.dynamic_uploader,
5971 &ice->state.last_res.color_calc,
5977 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
5978 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
5979 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
5980 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
6012 struct iris_shader_state *shs = &ice->state.shaders[stage];
6085 trace_framebuffer_state(&batch->trace, NULL, &ice->state.framebuffer);
6100 struct iris_shader_state *shs = &ice->state.shaders[stage];
6112 if (ice->state.need_border_colors)
6118 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
6119 if (ice->state.framebuffer.samples > 0)
6120 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
6126 ms.SampleMask = ice->state.sample_mask;
6145 UNUSED struct iris_rasterizer_state *cso = ice->state.cso_rast;
6146 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
6237 if (ice->state.streamout_active) {
6241 * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_* state is
6242 * not combined with other state changes.
6252 (void *) ice->state.so_target[i];
6288 if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) {
6290 * If SOL is enabled and SO_DECL state has to be programmed,
6291 * 1. Send 3D State SOL state with SOL disabled
6292 * 2. Send SO_DECL NP state
6299 ice->state.streamout + GENX(3DSTATE_STREAMOUT_length);
6304 const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
6312 !ice->state.prims_generated_query_active;
6316 assert(ice->state.streamout);
6318 iris_emit_merge(batch, ice->state.streamout, dynamic_sol,
6328 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
6329 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
6335 : ice->state.prim_is_points_or_lines);
6339 cl.StatisticsEnable = ice->state.statistics_counters_enabled;
6342 else if (ice->state.window_space_position)
6347 cl.PerspectiveDivideDisable = ice->state.window_space_position;
6353 cl.MaximumVPIndex = ice->state.num_viewports - 1;
6360 struct iris_rasterizer_state *cso = ice->state.cso_rast;
6365 sf.ViewportTransformEnable = !ice->state.window_space_position;
6368 sf.DerefBlockSize = ice->state.urb_deref_block_size;
6376 struct iris_rasterizer_state *cso = ice->state.cso_rast;
6380 wm.StatisticsEnable = ice->state.statistics_counters_enabled;
6404 struct iris_blend_state *cso_blend = ice->state.cso_blend;
6405 struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
6428 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
6430 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
6454 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
6470 * "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
6477 emit_state(batch, ice->state.dynamic_uploader,
6478 &ice->state.last_res.scissor,
6479 ice->state.scissors,
6481 ice->state.num_viewports, alignment);
6489 struct iris_depth_buffer_state *cso_z = &ice->state.genx->depth_buffer;
6492 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
6499 if (zres && ice->state.hiz_usage != ISL_AUX_USAGE_NONE) {
6520 * have an additional pipe control after the stencil state whenever
6521 * the surface state bits of this state is changing).
6525 iris_emit_pipe_control_write(batch, "WA for stencil state",
6534 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
6535 pin_depth_and_stencil_buffers(batch, cso_fb->zsbuf, ice->state.cso_zsa);
6541 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
6547 struct iris_rasterizer_state *cso = ice->state.cso_rast;
6554 translate_prim_type(draw->mode, ice->state.vertices_per_patch);
6559 int count = util_bitcount64(ice->state.bound_vertex_buffers);
6560 uint64_t dynamic_bound = ice->state.bound_vertex_buffers;
6562 if (ice->state.vs_uses_draw_params) {
6565 struct iris_vertex_buffer_state *state =
6566 &(ice->state.genx->vertex_buffers[count]);
6567 pipe_resource_reference(&state->resource, ice->draw.draw_params.res);
6568 struct iris_resource *res = (void *) state->resource;
6570 iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) {
6588 if (ice->state.vs_uses_derived_draw_params) {
6589 struct iris_vertex_buffer_state *state =
6590 &(ice->state.genx->vertex_buffers[count]);
6591 pipe_resource_reference(&state->resource,
6595 iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) {
6646 if (high_bits != ice->state.last_vbo_high_bits[i]) {
6649 ice->state.last_vbo_high_bits[i] = high_bits;
6673 memcpy(map, genx->vertex_buffers[i].state,
6681 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
6683 if (!(ice->state.vs_needs_sgvs_element ||
6684 ice->state.vs_uses_derived_draw_params ||
6685 ice->state.vs_needs_edge_flag)) {
6691 ice->state.vs_needs_sgvs_element +
6692 ice->state.vs_uses_derived_draw_params;
6700 (cso->count - ice->state.vs_needs_edge_flag) *
6703 &dynamic_ves[1 + (cso->count - ice->state.vs_needs_edge_flag) *
6706 if (ice->state.vs_needs_sgvs_element) {
6707 uint32_t base_ctrl = ice->state.vs_uses_draw_params ?
6712 util_bitcount64(ice->state.bound_vertex_buffers);
6721 if (ice->state.vs_uses_derived_draw_params) {
6725 util_bitcount64(ice->state.bound_vertex_buffers) +
6726 ice->state.vs_uses_draw_params;
6735 if (ice->state.vs_needs_edge_flag) {
6744 if (!ice->state.vs_needs_edge_flag) {
6758 ice->state.vs_needs_sgvs_element +
6759 ice->state.vs_uses_derived_draw_params;
6772 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
6779 cso->count - ice->state.vs_needs_edge_flag;
6786 cso->count - ice->state.vs_needs_edge_flag;
6846 if (ice->state.current_hash_scale != 1)
6857 struct iris_genx_state *genx = ice->state.genx;
6858 uint64_t bound = ice->state.bound_vertex_buffers;
6874 bool use_predicate = ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT;
6878 if (ice->state.dirty & IRIS_DIRTY_VERTEX_BUFFER_FLUSHES)
6888 iris_use_pinned_bo(batch, ice->state.binder.bo, false,
6898 ice->state.stage_dirty |= (IRIS_STAGE_DIRTY_CONSTANTS_VS |
6923 &offset, &ice->state.last_res.index_buffer);
6929 pipe_resource_reference(&ice->state.last_res.index_buffer,
6936 struct iris_genx_state *genx = ice->state.genx;
6937 struct iris_bo *bo = iris_resource_bo(ice->state.last_res.index_buffer);
6960 if (high_bits != ice->state.last_index_bo_high_bits) {
6965 ice->state.last_index_bo_high_bits = high_bits;
6989 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
7104 struct iris_state_ref *grid_size = &ice->state.grid_size;
7123 const uint64_t stage_dirty = ice->state.stage_dirty;
7126 struct iris_binder *binder = &ice->state.binder;
7127 struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
7188 const uint64_t stage_dirty = ice->state.stage_dirty;
7191 struct iris_binder *binder = &ice->state.binder;
7192 struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
7256 stream_state(batch, ice->state.dynamic_uploader,
7257 &ice->state.last_res.cs_thread_ids,
7272 struct pipe_resource *res = ice->state.global_bindings[i];
7305 emit_state(batch, ice->state.dynamic_uploader,
7306 &ice->state.last_res.cs_desc, desc, sizeof(desc), 64);
7341 const uint64_t stage_dirty = ice->state.stage_dirty;
7342 struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
7355 iris_use_pinned_bo(batch, ice->state.binder.bo, false, IRIS_DOMAIN_NONE);
7373 if (ice->state.need_border_colors)
7401 struct iris_genx_state *genx = ice->state.genx;
7403 pipe_resource_reference(&ice->state.pixel_hashing_tables, NULL);
7413 free(ice->state.genx);
7416 pipe_so_target_reference(&ice->state.so_target[i], NULL);
7419 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
7420 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
7422 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
7425 struct iris_shader_state *shs = &ice->state.shaders[stage];
7446 pipe_resource_reference(&ice->state.grid_size.res, NULL);
7447 pipe_resource_reference(&ice->state.grid_surf_state.res, NULL);
7449 pipe_resource_reference(&ice->state.null_fb.res, NULL);
7450 pipe_resource_reference(&ice->state.unbound_tex.res, NULL);
7452 pipe_resource_reference(&ice->state.last_res.cc_vp, NULL);
7453 pipe_resource_reference(&ice->state.last_res.sf_cl_vp, NULL);
7454 pipe_resource_reference(&ice->state.last_res.color_calc, NULL);
7455 pipe_resource_reference(&ice->state.last_res.scissor, NULL);
7456 pipe_resource_reference(&ice->state.last_res.blend, NULL);
7457 pipe_resource_reference(&ice->state.last_res.index_buffer, NULL);
7458 pipe_resource_reference(&ice->state.last_res.cs_thread_ids, NULL);
7459 pipe_resource_reference(&ice->state.last_res.cs_desc, NULL);
7469 struct iris_genx_state *genx = ice->state.genx;
7485 uint64_t bound_vbs = ice->state.bound_vertex_buffers;
7488 struct iris_vertex_buffer_state *state = &genx->vertex_buffers[i];
7493 uint64_t *addr = (uint64_t *) &state->state[1];
7494 struct iris_bo *bo = iris_resource_bo(state->resource);
7496 if (*addr != bo->address + state->offset) {
7497 *addr = bo->address + state->offset;
7498 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
7509 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
7522 struct pipe_stream_output_target *tgt = ice->state.so_target[i];
7527 ice->state.dirty |= IRIS_DIRTY_SO_BUFFERS;
7534 struct iris_shader_state *shs = &ice->state.shaders[s];
7551 ice->state.dirty |= (IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES |
7553 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS << s;
7583 if (update_surface_state_addrs(ice->state.surface_uploader,
7585 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_VS << s;
7597 if (update_surface_state_addrs(ice->state.surface_uploader,
7599 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_VS << s;
8222 struct iris_genx_state *genx = ice->state.genx;
8276 struct iris_genx_state *genx = ice->state.genx;
8384 ice->state.current_hash_scale = scale;
8395 ice->state.dirty |= IRIS_ALL_DIRTY_FOR_RENDER;
8396 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_FOR_RENDER;
8400 ice->state.dirty |= IRIS_ALL_DIRTY_FOR_COMPUTE;
8401 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE;
8491 ice->state.dirty = ~0ull;
8492 ice->state.stage_dirty = ~0ull;
8494 ice->state.statistics_counters_enabled = true;
8496 ice->state.sample_mask = 0xffff;
8497 ice->state.num_viewports = 1;
8498 ice->state.prim_mode = PIPE_PRIM_MAX;
8499 ice->state.genx = calloc(1, sizeof(struct iris_genx_state));
8504 upload_state(ice->state.surface_uploader, &ice->state.unbound_tex,
8508 ice->state.unbound_tex.offset +=
8509 iris_bo_offset_from_base_address(iris_resource_bo(ice->state.unbound_tex.res));
8513 ice->state.scissors[i] = (struct pipe_scissor_state) {