Lines Matching defs:flags
380 * (If so, we may want to set some dirty flags.)
894 .flags = IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE,
7611 * specified flags.
7614 batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
7620 if ((flags & PIPE_CONTROL_CS_STALL)) {
7621 if ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH))
7624 if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))
7627 if ((flags & PIPE_CONTROL_TILE_CACHE_FLUSH)) {
7635 if (flags & (PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_DATA_CACHE_FLUSH)) {
7640 if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH)) {
7646 if ((flags & PIPE_CONTROL_FLUSH_ENABLE))
7649 if ((flags & (PIPE_CONTROL_CACHE_FLUSH_BITS |
7658 if ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH))
7661 if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))
7664 if (flags & (PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_DATA_CACHE_FLUSH))
7667 if ((flags & PIPE_CONTROL_FLUSH_ENABLE))
7670 if ((flags & PIPE_CONTROL_VF_CACHE_INVALIDATE))
7673 if ((flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE))
7690 if ((flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE))
7695 if ((flags & PIPE_CONTROL_L3_RO_INVALIDATE_BITS) == PIPE_CONTROL_L3_RO_INVALIDATE_BITS) {
7707 flags_to_post_sync_op(uint32_t flags)
7709 if (flags & PIPE_CONTROL_WRITE_IMMEDIATE)
7712 if (flags & PIPE_CONTROL_WRITE_DEPTH_COUNT)
7715 if (flags & PIPE_CONTROL_WRITE_TIMESTAMP)
7722 * Do the given flags have a Post Sync or LRI Post Sync operation?
7725 get_post_sync_flags(enum pipe_control_flags flags)
7727 flags &= PIPE_CONTROL_WRITE_IMMEDIATE |
7735 assert(util_bitcount(flags) <= 1);
7737 return flags;
7757 uint32_t flags,
7763 enum pipe_control_flags post_sync_flags = get_post_sync_flags(flags);
7769 batch_mark_sync_for_pipe_control(batch, flags);
7772 assert(!(flags & PIPE_CONTROL_WRITE_DEPTH_COUNT));
7782 fd.PostSyncOperation = flags_to_post_sync_op(flags);
7802 if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)
7803 flags |= PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE;
7811 if (GFX_VER == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
7847 if (GFX_VER < 11 && flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) {
7854 flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
7862 if (flags & PIPE_CONTROL_DEPTH_STALL) {
7878 if (flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH |
7891 if (GFX_VER < 11 && (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD)) {
7905 assert(!(flags & (PIPE_CONTROL_DEPTH_STALL |
7911 if (GFX_VER <= 8 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) {
7919 flags |= PIPE_CONTROL_CS_STALL;
7922 if (flags & PIPE_CONTROL_FLUSH_LLC) {
7931 assert(flags & PIPE_CONTROL_WRITE_IMMEDIATE);
7946 assert((flags & PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET) == 0);
7948 if (flags & (PIPE_CONTROL_MEDIA_STATE_CLEAR |
7966 flags |= PIPE_CONTROL_CS_STALL;
7969 if (flags & PIPE_CONTROL_STORE_DATA_INDEX) {
7981 if (flags & PIPE_CONTROL_SYNC_GFDT) {
7992 if (flags & PIPE_CONTROL_TLB_INVALIDATE) {
8006 flags |= PIPE_CONTROL_CS_STALL;
8016 if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) {
8020 flags |= PIPE_CONTROL_CS_STALL;
8024 (flags & (PIPE_CONTROL_NOTIFY_ENABLE |
8042 flags |= PIPE_CONTROL_CS_STALL;
8068 if (GFX_VER < 9 && (flags & PIPE_CONTROL_CS_STALL)) {
8096 if (!(flags & wa_bits))
8097 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
8100 if (GFX_VER >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
8106 flags |= PIPE_CONTROL_DEPTH_STALL;
8114 (flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "",
8115 (flags & PIPE_CONTROL_CS_STALL) ? "CS " : "",
8116 (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) ? "Scoreboard " : "",
8117 (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) ? "VF " : "",
8118 (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) ? "RT " : "",
8119 (flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE) ? "Const " : "",
8120 (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE) ? "TC " : "",
8121 (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "",
8122 (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH) ? "ZFlush " : "",
8123 (flags & PIPE_CONTROL_TILE_CACHE_FLUSH) ? "Tile " : "",
8124 (flags & PIPE_CONTROL_DEPTH_STALL) ? "ZStall " : "",
8125 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "",
8126 (flags & PIPE_CONTROL_TLB_INVALIDATE) ? "TLB " : "",
8127 (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE) ? "Inst " : "",
8128 (flags & PIPE_CONTROL_MEDIA_STATE_CLEAR) ? "MediaClear " : "",
8129 (flags & PIPE_CONTROL_NOTIFY_ENABLE) ? "Notify " : "",
8130 (flags & PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET) ?
8132 (flags & PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE) ?
8134 (flags & PIPE_CONTROL_WRITE_IMMEDIATE) ? "WriteImm " : "",
8135 (flags & PIPE_CONTROL_WRITE_DEPTH_COUNT) ? "WriteZCount " : "",
8136 (flags & PIPE_CONTROL_WRITE_TIMESTAMP) ? "WriteTimestamp " : "",
8137 (flags & PIPE_CONTROL_FLUSH_HDC) ? "HDC " : "",
8138 (flags & PIPE_CONTROL_PSS_STALL_SYNC) ? "PSS " : "",
8142 batch_mark_sync_for_pipe_control(batch, flags);
8146 (flags & (PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CACHE_INVALIDATE_BITS)) != 0;
8153 pc.PSSStallSyncEnable = flags & PIPE_CONTROL_PSS_STALL_SYNC;
8156 pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH;
8159 pc.HDCPipelineFlushEnable = flags & PIPE_CONTROL_FLUSH_HDC;
8162 pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE;
8163 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
8165 pc.CommandStreamerStallEnable = flags & PIPE_CONTROL_CS_STALL;
8167 flags & PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET;
8168 pc.TLBInvalidate = flags & PIPE_CONTROL_TLB_INVALIDATE;
8169 pc.GenericMediaStateClear = flags & PIPE_CONTROL_MEDIA_STATE_CLEAR;
8170 pc.StallAtPixelScoreboard = flags & PIPE_CONTROL_STALL_AT_SCOREBOARD;
8172 flags & PIPE_CONTROL_RENDER_TARGET_FLUSH;
8173 pc.DepthCacheFlushEnable = flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH;
8175 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE;
8178 flags & PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE;
8180 pc.VFCacheInvalidationEnable = flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
8182 flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE;
8183 pc.PostSyncOperation = flags_to_post_sync_op(flags);
8184 pc.DepthStallEnable = flags & PIPE_CONTROL_DEPTH_STALL;
8186 flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE;
8187 pc.NotifyEnable = flags & PIPE_CONTROL_NOTIFY_ENABLE;
8189 flags & PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE;
8191 flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
8197 trace_intel_end_stall(&batch->trace, flags,