Lines Matching defs:devinfo
477 mi_builder_init(&b, &batch->screen->devinfo, batch);
486 mi_builder_init(&b, &batch->screen->devinfo, batch);
495 mi_builder_init(&b, &batch->screen->devinfo, batch);
504 mi_builder_init(&b, &batch->screen->devinfo, batch);
517 mi_builder_init(&b, &batch->screen->devinfo, batch);
533 mi_builder_init(&b, &batch->screen->devinfo, batch);
546 mi_builder_init(&b, &batch->screen->devinfo, batch);
563 mi_builder_init(&b, &batch->screen->devinfo, batch);
580 mi_builder_init(&b, &batch->screen->devinfo, batch);
594 mi_builder_init(&b, &batch->screen->devinfo, batch);
806 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
812 for (unsigned i = 2; i < ARRAY_SIZE(devinfo->ppipe_subslices); i++)
813 assert(devinfo->ppipe_subslices[i] == 0);
815 if (devinfo->ppipe_subslices[0] == devinfo->ppipe_subslices[1])
826 const bool flip = devinfo->ppipe_subslices[0] < devinfo->ppipe_subslices[1];
849 ppipes_of[n] += (devinfo->ppipe_subslices[p] == n);
853 for (unsigned p = 3; p < ARRAY_SIZE(devinfo->ppipe_subslices); p++)
854 assert(devinfo->ppipe_subslices[p] == 0);
911 for (unsigned p = 0; p < ARRAY_SIZE(devinfo->ppipe_subslices); p++) {
912 if (devinfo->ppipe_subslices[p])
956 const struct intel_device_info *devinfo = &batch->screen->devinfo;
969 const unsigned push_constant_kb = devinfo->max_constant_urb_size_kb;
988 if (intel_device_info_is_dg2(devinfo)) {
1062 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
1096 if (devinfo->platform == INTEL_PLATFORM_GLK)
1111 if (devinfo->disable_ccs_repack) {
1195 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
1220 if (devinfo->platform == INTEL_PLATFORM_GLK)
1633 UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
2154 UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
2536 const struct intel_device_info *devinfo = &screen->devinfo;
2568 iris_format_for_usage(devinfo, tmpl->format, usage);
2588 !isl_format_supports_ccs_e(devinfo, isv->view.format)) {
2591 !iris_sample_with_depth_aux(devinfo, isv->res)) {
2655 const struct intel_device_info *devinfo = &screen->devinfo;
2666 iris_format_for_usage(devinfo, tmpl->format, usage);
2669 !isl_format_supports_rendering(devinfo, fmt.fmt)) {
2794 !isl_format_supports_ccs_e(devinfo, view->format)) {
2977 UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
3696 const struct intel_device_info *devinfo = &screen->devinfo;
3726 iris_format_for_usage(devinfo, state[i].src_format, 0);
3767 iris_format_for_usage(devinfo, state[edgeflag_index].src_format, 0);
4510 iris_store_vs_state(const struct intel_device_info *devinfo,
4518 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
4529 iris_store_tcs_state(const struct intel_device_info *devinfo,
4546 assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances);
4552 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
4573 iris_store_tes_state(const struct intel_device_info *devinfo,
4587 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
4622 iris_store_gs_state(const struct intel_device_info *devinfo,
4643 GFX_VER == 8 ? (devinfo->max_gs_threads / 2 - 1)
4644 : (devinfo->max_gs_threads - 1);
4669 iris_store_fs_state(const struct intel_device_info *devinfo,
4683 devinfo->max_threads_per_psd - (GFX_VER == 8 ? 2 : 1);
4731 iris_store_cs_state(const struct intel_device_info *devinfo,
4789 iris_store_derived_program_state(const struct intel_device_info *devinfo,
4795 iris_store_vs_state(devinfo, shader);
4798 iris_store_tcs_state(devinfo, shader);
4801 iris_store_tes_state(devinfo, shader);
4804 iris_store_gs_state(devinfo, shader);
4807 iris_store_fs_state(devinfo, shader);
4810 iris_store_cs_state(devinfo, shader);
5909 intel_get_urb_config(&screen->devinfo,
6244 if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
6281 if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
6295 if (intel_device_info_is_dg2(&batch->screen->devinfo))
6812 if (intel_device_info_is_dg2(&batch->screen->devinfo))
6978 mi_builder_init(&b, &batch->screen->devinfo, batch);
7107 mi_builder_init(&b, &batch->screen->devinfo, batch);
7125 const struct intel_device_info *devinfo = &screen->devinfo;
7133 brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
7140 devinfo->max_cs_threads * devinfo->subslice_total;
7190 const struct intel_device_info *devinfo = &screen->devinfo;
7200 brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
7229 devinfo->max_cs_threads * devinfo->subslice_total - 1;
7616 const struct intel_device_info *devinfo = &batch->screen->devinfo;
7700 if (!iris_domain_is_l3_coherent(devinfo, i))
7762 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
8009 if (GFX_VER == 9 && devinfo->gt == 4) {
8322 const struct intel_device_info *devinfo = &batch->screen->devinfo;
8378 reg.SliceHashing = (devinfo->num_slices > 1 ? slice_hashing[idx] : 0);
8379 reg.SliceHashingMask = (devinfo->num_slices > 1 ? -1 : 0);
8408 assert(screen->devinfo.verx10 == GFX_VERx10);