Lines Matching defs:batch
59 * we can simply memcpy them into a batch buffer.
70 * the context state and emit the commands into the actual batch.
334 stream_state(struct iris_batch *batch,
346 iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
348 iris_record_state_size(batch->state_sizes,
360 emit_state(struct iris_batch *batch,
369 stream_state(batch, uploader, out_res, size, alignment, &offset);
387 flush_before_state_base_change(struct iris_batch *batch)
398 * and flushes prior to executing our batch. However, it doesn't seem
410 iris_emit_end_of_pipe_sync(batch,
418 flush_after_state_base_change(struct iris_batch *batch)
463 iris_emit_end_of_pipe_sync(batch,
473 iris_load_register_reg32(struct iris_batch *batch, uint32_t dst,
477 mi_builder_init(&b, &batch->screen->devinfo, batch);
482 iris_load_register_reg64(struct iris_batch *batch, uint32_t dst,
486 mi_builder_init(&b, &batch->screen->devinfo, batch);
491 iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
495 mi_builder_init(&b, &batch->screen->devinfo, batch);
500 iris_load_register_imm64(struct iris_batch *batch, uint32_t reg,
504 mi_builder_init(&b, &batch->screen->devinfo, batch);
512 iris_load_register_mem32(struct iris_batch *batch, uint32_t reg,
515 iris_batch_sync_region_start(batch);
517 mi_builder_init(&b, &batch->screen->devinfo, batch);
520 iris_batch_sync_region_end(batch);
528 iris_load_register_mem64(struct iris_batch *batch, uint32_t reg,
531 iris_batch_sync_region_start(batch);
533 mi_builder_init(&b, &batch->screen->devinfo, batch);
536 iris_batch_sync_region_end(batch);
540 iris_store_register_mem32(struct iris_batch *batch, uint32_t reg,
544 iris_batch_sync_region_start(batch);
546 mi_builder_init(&b, &batch->screen->devinfo, batch);
553 iris_batch_sync_region_end(batch);
557 iris_store_register_mem64(struct iris_batch *batch, uint32_t reg,
561 iris_batch_sync_region_start(batch);
563 mi_builder_init(&b, &batch->screen->devinfo, batch);
570 iris_batch_sync_region_end(batch);
574 iris_store_data_imm32(struct iris_batch *batch,
578 iris_batch_sync_region_start(batch);
580 mi_builder_init(&b, &batch->screen->devinfo, batch);
584 iris_batch_sync_region_end(batch);
588 iris_store_data_imm64(struct iris_batch *batch,
592 iris_batch_sync_region_start(batch);
594 mi_builder_init(&b, &batch->screen->devinfo, batch);
598 iris_batch_sync_region_end(batch);
602 iris_copy_mem_mem(struct iris_batch *batch,
611 iris_batch_sync_region_start(batch);
614 iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) {
621 iris_batch_sync_region_end(batch);
625 emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline)
638 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
652 iris_emit_pipe_control_flush(batch,
659 iris_emit_pipe_control_flush(batch,
666 iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
676 init_glk_barrier_mode(struct iris_batch *batch, uint32_t value)
686 iris_emit_reg(batch, GENX(SLICE_COMMON_ECO_CHICKEN1), reg) {
694 init_state_base_address(struct iris_batch *batch)
696 struct isl_device *isl_dev = &batch->screen->isl_dev;
698 flush_before_state_base_change(batch);
707 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
744 flush_after_state_base_change(batch);
748 iris_emit_l3_config(struct iris_batch *batch,
761 iris_emit_reg(batch, L3_ALLOCATION_REG, reg) {
788 iris_enable_obj_preemption(struct iris_batch *batch, bool enable)
791 iris_emit_end_of_pipe_sync(batch, enable ? "enable preemption"
796 iris_emit_reg(batch, GENX(CS_CHICKEN1), reg) {
804 upload_pixel_hashing_tables(struct iris_batch *batch)
806 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
807 UNUSED struct iris_context *ice = batch->ice;
808 assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
822 stream_state(batch, ice->state.dynamic_uploader, &tmp,
832 iris_emit_cmd(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
837 iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), mode) {
863 iris_emit_cmd(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {
881 iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), p) {
887 struct pipe_screen *pscreen = &batch->screen->base;
934 iris_use_pinned_bo(batch, res->bo, false, IRIS_DOMAIN_NONE);
935 iris_record_state_size(batch->state_sizes, res->bo->address + res->offset, size);
937 iris_emit_cmd(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
943 iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), mode) {
954 iris_alloc_push_constants(struct iris_batch *batch)
956 const struct intel_device_info *devinfo = &batch->screen->devinfo;
974 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
989 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_ALL), c) {
992 c.MOCS = iris_mocs(NULL, &batch->screen->isl_dev, 0);
1000 init_aux_map_state(struct iris_batch *batch);
1005 iris_disable_rhwo_optimization(struct iris_batch *batch, bool disable)
1008 iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
1021 iris_init_common_context(struct iris_batch *batch)
1024 iris_emit_reg(batch, GENX(SAMPLER_MODE), reg) {
1030 iris_emit_reg(batch, GENX(HALF_SLICE_CHICKEN7), reg) {
1043 iris_emit_reg(batch, GENX(GT_MODE), reg) {
1060 iris_init_render_context(struct iris_batch *batch)
1062 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
1064 iris_batch_sync_region_start(batch);
1066 emit_pipeline_select(batch, _3D);
1068 iris_emit_l3_config(batch, batch->screen->l3_config_3d);
1070 init_state_base_address(batch);
1072 iris_init_common_context(batch);
1075 iris_emit_reg(batch, GENX(CS_DEBUG_MODE2), reg) {
1080 iris_emit_reg(batch, GENX(INSTPM), reg) {
1087 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) {
1097 init_glk_barrier_mode(batch, GLK_BARRIER_MODE_3D_HULL);
1101 iris_emit_reg(batch, GENX(TCCNTLREG), reg) {
1112 iris_emit_reg(batch, GENX(CACHE_MODE_0), reg) {
1134 iris_disable_rhwo_optimization(batch, true);
1140 iris_emit_reg(batch, GENX(HIZ_CHICKEN), reg) {
1146 upload_pixel_hashing_tables(batch);
1153 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
1159 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
1170 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
1173 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
1176 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
1180 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
1182 iris_alloc_push_constants(batch);
1186 init_aux_map_state(batch);
1189 iris_batch_sync_region_end(batch);
1193 iris_init_compute_context(struct iris_batch *batch)
1195 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
1197 iris_batch_sync_region_start(batch);
1204 emit_pipeline_select(batch, _3D);
1206 emit_pipeline_select(batch, GPGPU);
1209 iris_emit_l3_config(batch, batch->screen->l3_config_cs);
1211 init_state_base_address(batch);
1213 iris_init_common_context(batch);
1216 emit_pipeline_select(batch, GPGPU);
1221 init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU);
1225 init_aux_map_state(batch);
1228 iris_batch_sync_region_end(batch);
1753 struct iris_batch *batch,
1772 iris_emit_pipe_control_flush(batch, "PMA fix change (1/2)",
1777 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) {
1791 iris_emit_pipe_control_flush(batch, "PMA fix change (1/2)",
4171 iris_emit_sbe_swiz(struct iris_batch *batch,
4255 iris_emit_cmd(batch, GENX(3DSTATE_SBE_SWIZ), sbes) {
4302 iris_emit_sbe(struct iris_batch *batch, const struct iris_context *ice)
4320 iris_emit_cmd(batch, GENX(3DSTATE_SBE), sbe) {
4350 iris_emit_sbe_swiz(batch, ice, last_vue_map, urb_read_offset,
4486 _iris_pack_command(batch, GENX(name), pkt2, p) { \
4489 iris_emit_merge(batch, pkt, pkt2, GENX(name##_length)); \
4497 _iris_pack_command(batch, GENX(name), pkt2, p) { \
4501 iris_emit_merge(batch, pkt, pkt2, GENX(name##_length)); \
4829 use_null_surface(struct iris_batch *batch, struct iris_context *ice)
4833 iris_use_pinned_bo(batch, state_bo, false, IRIS_DOMAIN_NONE);
4839 use_null_fb_surface(struct iris_batch *batch, struct iris_context *ice)
4843 return use_null_surface(batch, ice);
4847 iris_use_pinned_bo(batch, state_bo, false, IRIS_DOMAIN_NONE);
4863 surf_state_update_clear_value(struct iris_batch *batch,
4868 struct isl_device *isl_dev = &batch->screen->isl_dev;
4880 iris_emit_pipe_control_write(batch, "update fast clear value (Z)",
4884 iris_emit_pipe_control_write(batch, "update fast clear color (RG__)",
4889 iris_emit_pipe_control_write(batch, "update fast clear color (__BA)",
4896 iris_emit_pipe_control_flush(batch,
4905 struct iris_batch *batch,
4910 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
4923 surf_state_update_clear_value(batch, res, surf_state, aux_usage);
4936 use_surface_state(struct iris_batch *batch,
4940 iris_use_pinned_bo(batch, iris_resource_bo(surf_state->ref.res), false,
4955 struct iris_batch *batch,
4977 update_clear_value(ice, batch, res, &surf->surface_state, &surf->view);
4979 update_clear_value(ice, batch, res, &surf->surface_state_read,
4986 iris_use_pinned_bo(batch, res->aux.clear_color_bo, false, access);
4989 iris_use_pinned_bo(batch, res->aux.bo, writeable, access);
4991 iris_use_pinned_bo(batch, res->bo, writeable, access);
4994 return use_surface_state(batch, &surf->surface_state_read, aux_usage);
4996 return use_surface_state(batch, &surf->surface_state, aux_usage);
5002 struct iris_batch *batch,
5013 update_clear_value(ice, batch, isv->res, &isv->surface_state,
5019 iris_use_pinned_bo(batch, isv->res->aux.clear_color_bo,
5024 iris_use_pinned_bo(batch, isv->res->aux.bo,
5028 iris_use_pinned_bo(batch, isv->res->bo, false, IRIS_DOMAIN_SAMPLER_READ);
5030 return use_surface_state(batch, &isv->surface_state, aux_usage);
5034 use_ubo_ssbo(struct iris_batch *batch,
5041 return use_null_surface(batch, ice);
5043 iris_use_pinned_bo(batch, iris_resource_bo(buf->buffer), writable, access);
5044 iris_use_pinned_bo(batch, iris_resource_bo(surf_state->res), false,
5051 use_image(struct iris_batch *batch, struct iris_context *ice,
5059 return use_null_surface(batch, ice);
5063 iris_use_pinned_bo(batch, res->bo, write, IRIS_DOMAIN_NONE);
5066 iris_use_pinned_bo(batch, res->aux.bo, write, IRIS_DOMAIN_NONE);
5071 return use_surface_state(batch, &iv->surface_state, aux_usage);
5088 * resident before running our batch.
5092 struct iris_batch *batch,
5121 iris_use_pinned_bo(batch, iris_resource_bo(grid_data->res), false,
5123 iris_use_pinned_bo(batch, iris_resource_bo(grid_state->res), false,
5135 addr = use_surface(ice, batch, cso_fb->cbufs[i], true,
5139 addr = use_null_fb_surface(batch, ice);
5144 uint32_t addr = use_null_fb_surface(batch, ice);
5159 addr = use_surface(ice, batch, cso_fb->cbufs[i],
5168 uint32_t addr = view ? use_sampler_view(ice, batch, view)
5169 : use_null_surface(batch, ice);
5174 uint32_t addr = use_image(batch, ice, shs, info, i);
5179 uint32_t addr = use_ubo_ssbo(batch, ice, &shs->constbuf[i],
5187 use_ubo_ssbo(batch, ice, &shs->ssbo[i], &shs->ssbo_surf_state[i],
5200 iris_use_optional_res(struct iris_batch *batch,
5207 iris_use_pinned_bo(batch, bo, writeable, access);
5212 pin_depth_and_stencil_buffers(struct iris_batch *batch,
5223 iris_use_pinned_bo(batch, zres->bo, cso_zsa->depth_writes_enabled,
5226 iris_use_pinned_bo(batch, zres->aux.bo,
5233 iris_use_pinned_bo(batch, sres->bo, cso_zsa->stencil_writes_enabled,
5240 struct iris_batch *batch,
5249 iris_use_pinned_bo(batch, scratch_bo, true, IRIS_DOMAIN_NONE);
5254 iris_use_pinned_bo(batch, iris_resource_bo(ref->res),
5271 * Pin any BOs which were installed by a previous batch, and restored
5274 * We don't need to re-emit all state every batch - the hardware context
5285 struct iris_batch *batch,
5294 iris_use_optional_res(batch, ice->state.last_res.cc_vp, false,
5299 iris_use_optional_res(batch, ice->state.last_res.sf_cl_vp, false,
5304 iris_use_optional_res(batch, ice->state.last_res.blend, false,
5309 iris_use_optional_res(batch, ice->state.last_res.color_calc, false,
5314 iris_use_optional_res(batch, ice->state.last_res.scissor, false,
5323 iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer),
5325 iris_use_pinned_bo(batch, iris_resource_bo(tgt->offset.res),
5358 iris_use_pinned_bo(batch, res->bo, false, IRIS_DOMAIN_OTHER_READ);
5360 iris_use_pinned_bo(batch, batch->screen->workaround_bo, false,
5368 iris_populate_binding_table(ice, batch, stage, true);
5376 iris_use_pinned_bo(batch, iris_resource_bo(res), false,
5386 iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
5388 pin_scratch_space(ice, batch, shader->prog_data, stage);
5396 pin_depth_and_stencil_buffers(batch, cso_fb->zsbuf, ice->state.cso_zsa);
5399 iris_use_optional_res(batch, ice->state.last_res.index_buffer, false,
5407 iris_use_pinned_bo(batch, iris_resource_bo(res), false,
5413 iris_use_pinned_bo(batch, iris_resource_bo(ice->state.pixel_hashing_tables),
5422 struct iris_batch *batch,
5432 iris_populate_binding_table(ice, batch, stage, true);
5437 iris_use_pinned_bo(batch, iris_resource_bo(sampler_res), false,
5444 iris_use_optional_res(batch, ice->state.last_res.cs_desc, false,
5453 iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
5458 iris_use_pinned_bo(batch, curbe_bo, false, IRIS_DOMAIN_NONE);
5461 pin_scratch_space(ice, batch, shader->prog_data, stage);
5470 iris_update_binder_address(struct iris_batch *batch,
5473 if (batch->last_binder_address == binder->bo->address)
5476 struct isl_device *isl_dev = &batch->screen->isl_dev;
5479 iris_batch_sync_region_start(batch);
5490 if (batch->name == IRIS_BATCH_COMPUTE)
5491 emit_pipeline_select(batch, _3D);
5494 iris_emit_pipe_control_flush(batch, "Stall for binder realloc",
5497 iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POOL_ALLOC), btpa) {
5511 if (batch->name == IRIS_BATCH_COMPUTE)
5512 emit_pipeline_select(batch, GPGPU);
5516 flush_before_state_base_change(batch);
5518 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
5537 flush_after_state_base_change(batch);
5538 iris_batch_sync_region_end(batch);
5540 batch->last_binder_address = binder->bo->address;
5557 genX(invalidate_aux_map_state)(struct iris_batch *batch)
5559 struct iris_screen *screen = batch->screen;
5564 if (batch->last_aux_map_state != aux_map_state_num) {
5574 iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
5582 iris_load_register_imm32(batch, GENX(GFX_CCS_AUX_INV_num), 1);
5583 batch->last_aux_map_state = aux_map_state_num;
5588 init_aux_map_state(struct iris_batch *batch)
5590 struct iris_screen *screen = batch->screen;
5597 iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num),
5613 struct iris_batch *batch,
5646 iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_OTHER_READ);
5651 : batch->screen->workaround_address;
5667 struct iris_batch *batch,
5671 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5675 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
5709 struct iris_batch *batch,
5713 struct isl_device *isl_dev = &batch->screen->isl_dev;
5716 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_ALL), pc) {
5739 _iris_pack_state(batch, GENX(3DSTATE_CONSTANT_ALL_DATA),
5745 iris_batch_emit(batch, const_all, sizeof(uint32_t) * num_dwords);
5751 struct iris_batch *batch,
5775 iris_emit_end_of_pipe_sync(batch,
5785 iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), reg) {
5798 struct iris_batch *batch,
5801 struct iris_screen *screen = batch->screen;
5822 stream_state(batch, ice->state.dynamic_uploader,
5844 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
5853 stream_state(batch, ice->state.dynamic_uploader,
5892 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
5920 iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
5944 stream_state(batch, ice->state.dynamic_uploader,
5957 iris_emit_cmd(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) {
5970 stream_state(batch, ice->state.dynamic_uploader,
5986 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
6022 setup_constant_buffers(ice, batch, stage, &push_bos);
6038 emit_push_constant_packet_all(ice, batch, 1 << stage, &push_bos);
6042 emit_push_constant_packets(ice, batch, stage, &push_bos);
6047 emit_push_constant_packet_all(ice, batch, nobuffer_stages, NULL);
6058 iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) {
6079 iris_emit_pipe_control_flush(batch, "workaround: RT BTI change [draw]",
6085 trace_framebuffer_state(&batch->trace, NULL, &ice->state.framebuffer);
6089 iris_populate_binding_table(ice, batch, stage, false);
6103 iris_use_pinned_bo(batch, iris_resource_bo(res), false,
6106 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
6113 iris_use_pinned_bo(batch, border_color_pool->bo, false, IRIS_DOMAIN_NONE);
6116 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
6125 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
6139 iris_use_pinned_bo(batch, cache->bo, false, IRIS_DOMAIN_NONE);
6142 pin_scratch_space(ice, batch, prog_data, stage);
6149 _iris_pack_command(batch, GENX(3DSTATE_PS), ps_state, ps) {
6210 iris_emit_merge(batch, shader_ps, ps_state,
6212 iris_emit_merge(batch, shader_psx, psx_state,
6223 iris_batch_emit(batch, shader->derived_data,
6228 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs);
6229 iris_emit_cmd(batch, GENX(3DSTATE_TE), te);
6230 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds);
6232 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs);
6244 if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
6245 iris_emit_pipe_control_flush(batch,
6259 iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer),
6261 iris_use_pinned_bo(batch, iris_resource_bo(tgt->offset.res),
6272 iris_batch_emit(batch, so_buffers, 4 * (dwords - 1));
6273 iris_batch_emit(batch, &zero, sizeof(zero));
6276 iris_batch_emit(batch, so_buffers, 4 * dwords);
6281 if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
6282 iris_emit_pipe_control_flush(batch,
6295 if (intel_device_info_is_dg2(&batch->screen->devinfo))
6296 iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol);
6300 iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2));
6318 iris_emit_merge(batch, ice->state.streamout, dynamic_sol,
6323 iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol);
6355 iris_emit_merge(batch, cso_rast->clip, dynamic_clip,
6361 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
6371 iris_emit_merge(batch, cso->sf, dynamic_sf,
6396 iris_emit_merge(batch, cso->wm, dynamic_wm, ARRAY_SIZE(cso->wm));
6400 iris_emit_sbe(batch, ice);
6423 iris_emit_merge(batch, cso_blend->ps_blend, dynamic_pb,
6436 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
6441 iris_batch_emit(batch, cso->wmds, sizeof(cso->wmds));
6445 iris_batch_emit(batch, cso->depth_bounds, sizeof(cso->depth_bounds));
6464 iris_batch_emit(batch, stencil_refs, sizeof(stencil_refs));
6477 emit_state(batch, ice->state.dynamic_uploader,
6483 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
6510 iris_batch_emit(batch, cso_z->packets, sizeof(cso_z->packets));
6513 genX(emit_depth_state_workarounds)(ice, batch, &zres->surf);
6525 iris_emit_pipe_control_write(batch, "WA for stencil state",
6535 pin_depth_and_stencil_buffers(batch, cso_fb->zsbuf, ice->state.cso_zsa);
6539 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
6548 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
6552 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
6620 iris_use_optional_res(batch, genx->vertex_buffers[i].resource,
6628 * you can get collisions (even within a single batch).
6643 iris_use_pinned_bo(batch, res->bo, false, IRIS_DOMAIN_VF_READ);
6655 iris_emit_pipe_control_flush(batch,
6664 iris_get_command_space(batch, 4 * (1 + vb_dwords * count));
6665 _iris_pack_command(batch, GENX(3DSTATE_VERTEX_BUFFERS), map, vb) {
6686 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
6740 iris_batch_emit(batch, &dynamic_ves, sizeof(uint32_t) *
6745 iris_batch_emit(batch, cso->vf_instancing, sizeof(uint32_t) *
6764 iris_batch_emit(batch, &dynamic_vfi[0], sizeof(uint32_t) *
6774 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgv) {
6792 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
6805 iris_emit_cmd(batch, GENX(3DSTATE_VFG), vfg) {
6812 if (intel_device_info_is_dg2(&batch->screen->devinfo))
6834 iris_emit_cmd(batch, GENX(3DSTATE_VF_STATISTICS), vf) {
6842 genX(update_pma_fix)(ice, batch, enable);
6847 genX(emit_hashing_mode)(ice, batch, UINT_MAX, UINT_MAX, 1);
6850 genX(invalidate_aux_map_state)(batch);
6855 flush_vbos(struct iris_context *ice, struct iris_batch *batch)
6862 iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_VF_READ);
6868 struct iris_batch *batch,
6876 trace_intel_begin_draw(&batch->trace);
6879 flush_vbos(ice, batch);
6881 iris_batch_sync_region_start(batch);
6888 iris_use_pinned_bo(batch, ice->state.binder.bo, false,
6891 if (!batch->contains_draw) {
6893 /* Re-emit constants when starting a new batch buffer in order to
6904 batch->contains_draw = true;
6907 if (!batch->contains_draw_with_next_seqno) {
6908 iris_restore_render_saved_bos(ice, batch, draw);
6909 batch->contains_draw_with_next_seqno = true;
6912 iris_upload_dirty_render_state(ice, batch, draw);
6933 iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_VF_READ);
6942 ib.MOCS = iris_mocs(bo, &batch->screen->isl_dev,
6953 iris_batch_emit(batch, ib_packet, sizeof(ib_packet));
6954 iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_VF_READ);
6961 iris_emit_pipe_control_flush(batch,
6978 mi_builder_init(&b, &batch->screen->devinfo, batch);
7026 iris_batch_emit(batch, &mi_predicate, sizeof(uint32_t));
7053 iris_emit_buffer_barrier_for(batch, so_bo, IRIS_DOMAIN_OTHER_READ);
7067 iris_measure_snapshot(ice, batch, INTEL_SNAPSHOT_DRAW, draw, indirect, sc);
7069 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
7088 iris_batch_sync_region_end(batch);
7090 trace_intel_end_draw(&batch->trace, 0);
7095 struct iris_batch *batch,
7107 mi_builder_init(&b, &batch->screen->devinfo, batch);
7120 struct iris_batch *batch,
7124 struct iris_screen *screen = batch->screen;
7135 trace_intel_begin_compute(&batch->trace);
7138 iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
7141 uint32_t scratch_addr = pin_scratch_space(ice, batch, prog_data,
7148 iris_load_indirect_location(ice, batch, grid);
7150 iris_measure_snapshot(ice, batch, INTEL_SNAPSHOT_COMPUTE, NULL, NULL, NULL);
7152 iris_emit_cmd(batch, GENX(COMPUTE_WALKER), cw) {
7178 trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2]);
7185 struct iris_batch *batch,
7189 struct iris_screen *screen = batch->screen;
7202 trace_intel_begin_compute(&batch->trace);
7214 iris_emit_pipe_control_flush(batch,
7218 iris_emit_cmd(batch, GENX(MEDIA_VFE_STATE), vfe) {
7221 pin_scratch_space(ice, batch, prog_data, MESA_SHADER_COMPUTE);
7256 stream_state(batch, ice->state.dynamic_uploader,
7265 iris_emit_cmd(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
7276 iris_use_pinned_bo(batch, iris_resource_bo(res),
7301 iris_emit_cmd(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), load) {
7305 emit_state(batch, ice->state.dynamic_uploader,
7311 iris_load_indirect_location(ice, batch, grid);
7313 iris_measure_snapshot(ice, batch, INTEL_SNAPSHOT_COMPUTE, NULL, NULL, NULL);
7315 iris_emit_cmd(batch, GENX(GPGPU_WALKER), ggw) {
7328 iris_emit_cmd(batch, GENX(MEDIA_STATE_FLUSH), msf);
7330 trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2]);
7337 struct iris_batch *batch,
7340 struct iris_screen *screen = batch->screen;
7348 iris_batch_sync_region_start(batch);
7355 iris_use_pinned_bo(batch, ice->state.binder.bo, false, IRIS_DOMAIN_NONE);
7363 iris_populate_binding_table(ice, batch, MESA_SHADER_COMPUTE, false);
7368 iris_use_optional_res(batch, shs->sampler_table.res, false,
7370 iris_use_pinned_bo(batch, iris_resource_bo(shader->assembly.res), false,
7374 iris_use_pinned_bo(batch, border_color_pool->bo, false,
7378 genX(invalidate_aux_map_state)(batch);
7382 iris_upload_compute_walker(ice, batch, grid);
7384 iris_upload_gpgpu_walker(ice, batch, grid);
7387 if (!batch->contains_draw_with_next_seqno) {
7388 iris_restore_compute_saved_bos(ice, batch, grid);
7389 batch->contains_draw_with_next_seqno = batch->contains_draw = true;
7392 iris_batch_sync_region_end(batch);
7609 * Introduce a batch synchronization boundary, and update its cache coherency
7614 batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
7616 const struct intel_device_info *devinfo = &batch->screen->devinfo;
7618 iris_batch_sync_boundary(batch);
7622 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_RENDER_WRITE);
7625 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_DEPTH_WRITE);
7631 batch->coherent_seqnos[c][c] = batch->l3_coherent_seqnos[c];
7632 batch->coherent_seqnos[z][z] = batch->l3_coherent_seqnos[z];
7637 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_DATA_WRITE);
7643 batch->coherent_seqnos[i][i] = batch->l3_coherent_seqnos[i];
7647 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_WRITE);
7651 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_VF_READ);
7652 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_SAMPLER_READ);
7653 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_PULL_CONSTANT_READ);
7654 iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_READ);
7659 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_RENDER_WRITE);
7662 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DEPTH_WRITE);
7665 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DATA_WRITE);
7668 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_WRITE);
7671 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_VF_READ);
7674 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_SAMPLER_READ);
7691 iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_PULL_CONSTANT_READ);
7701 batch->l3_coherent_seqnos[i] = batch->coherent_seqnos[i][i];
7740 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
7755 iris_emit_raw_pipe_control(struct iris_batch *batch,
7762 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
7768 if (batch->name == IRIS_BATCH_BLITTER) {
7769 batch_mark_sync_for_pipe_control(batch, flags);
7770 iris_batch_sync_region_start(batch);
7779 iris_emit_cmd(batch, GENX(MI_FLUSH_DW), fd) {
7788 iris_batch_sync_region_end(batch);
7823 iris_emit_raw_pipe_control(batch,
7828 if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
7838 iris_emit_raw_pipe_control(batch,
7857 bo = batch->screen->workaround_address.bo;
7858 offset = batch->screen->workaround_address.offset;
8015 if (IS_COMPUTE_PIPELINE(batch)) {
8142 batch_mark_sync_for_pipe_control(batch, flags);
8143 iris_batch_sync_region_start(batch);
8149 trace_intel_begin_stall(&batch->trace);
8151 iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) {
8197 trace_intel_end_stall(&batch->trace, flags,
8202 iris_batch_sync_region_end(batch);
8219 struct iris_batch *batch,
8267 iris_enable_obj_preemption(batch, object_preemption);
8274 iris_lost_genx_state(struct iris_context *ice, struct iris_batch *batch)
8286 iris_emit_mi_report_perf_count(struct iris_batch *batch,
8291 iris_batch_sync_region_start(batch);
8292 iris_emit_cmd(batch, GENX(MI_REPORT_PERF_COUNT), mi_rpc) {
8297 iris_batch_sync_region_end(batch);
8318 genX(emit_hashing_mode)(struct iris_context *ice, struct iris_batch *batch,
8322 const struct intel_device_info *devinfo = &batch->screen->devinfo;
8371 iris_emit_raw_pipe_control(batch,
8377 iris_emit_reg(batch, GENX(GT_MODE), reg) {