Lines Matching refs:sc
137 static int axe_miibus_writereg(struct axe_softc *sc, int reg, int val);
138 static uint16_t axe_miibus_readreg(struct axe_softc *sc, int reg);
220 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
225 AXE_LOCK_ASSERT(sc, MA_OWNED);
235 err = uether_do_request(&sc->sc_ue, &req, buf, 10000);
242 axe_miibus_readreg(struct axe_softc *sc, int reg)
246 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
247 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, 0x10, &val);
248 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
251 if (AXE_IS_772(sc) && reg == MII_BMSR) {
264 axe_miibus_writereg(struct axe_softc *sc, int reg, int val)
268 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
269 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, 0x10, &val);
270 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
275 axe_setmedium(struct axe_softc *sc)
282 bmcr = axe_miibus_readreg(sc, 0);
304 axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
314 axe_get_phyno(struct axe_softc *sc, int sel)
318 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
321 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
344 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
349 axe_ax88178_init(struct axe_softc *sc)
355 ue = &sc->sc_ue;
356 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
358 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
360 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
430 (void) axe_miibus_writereg(sc, 0x1F, 0x0005);
431 (void) axe_miibus_writereg(sc, 0x0C, 0x0000);
432 val = axe_miibus_readreg(sc, 0x0001);
433 (void) axe_miibus_writereg(sc, 0x01, val | 0x0080);
434 (void) axe_miibus_writereg(sc, 0x1F, 0x0000);
443 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
446 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
450 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
453 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
457 axe_ax88772_init(struct axe_softc *sc)
459 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
460 axe_uether_pause(&sc->sc_ue, hz / 16);
462 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
464 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
465 axe_uether_pause(&sc->sc_ue, hz / 64);
468 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
470 axe_uether_pause(&sc->sc_ue, hz / 16);
473 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
475 axe_uether_pause(&sc->sc_ue, hz / 4);
478 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
481 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
485 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
486 axe_uether_pause(&sc->sc_ue, hz / 64);
489 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
493 axe_uether_pause(&sc->sc_ue, hz / 4);
494 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
498 axe_ax88772_phywake(struct axe_softc *sc)
500 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
502 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
505 axe_uether_pause(&sc->sc_ue, hz / 32);
511 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
513 axe_uether_pause(&sc->sc_ue, hz / 32);
516 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
518 axe_uether_pause(&sc->sc_ue, hz / 4);
519 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
520 axe_uether_pause(&sc->sc_ue, hz);
521 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
522 axe_uether_pause(&sc->sc_ue, hz / 32);
523 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
524 axe_uether_pause(&sc->sc_ue, hz / 32);
528 axe_ax88772b_init(struct axe_softc *sc)
530 struct usb_ether *ue = &sc->sc_ue;
543 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
544 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
555 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, &eeprom);
562 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, ue->ue_eaddr);
567 axe_ax88772_phywake(sc);
569 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
574 sc->sc_flags &= ~AXE_FLAG_LINK;
576 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
582 axe_reset(struct axe_softc *sc)
587 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
588 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
594 axe_uether_pause(&sc->sc_ue, hz / 100);
596 if (sc->sc_flags & AXE_FLAG_178)
597 axe_ax88178_init(sc);
598 else if (sc->sc_flags & AXE_FLAG_772)
599 axe_ax88772_init(sc);
600 else if (sc->sc_flags & AXE_FLAG_772A)
601 axe_ax88772b_init(sc);
602 else if (sc->sc_flags & AXE_FLAG_772B)
603 axe_ax88772b_init(sc);
605 axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0,
613 struct axe_softc *sc = uether_getsc(ue);
617 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
618 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
619 if (sc->sc_phyno == -1)
620 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
621 if (sc->sc_phyno == -1) {
622 device_printf(sc->sc_ue.ue_dev,
624 sc->sc_phyno = 0;
629 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
631 sc->sc_ipgs[0] = 0x15;
632 sc->sc_ipgs[1] = 0x16;
633 sc->sc_ipgs[2] = 0x1A;
635 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
655 axe_miibus_statchg(struct axe_softc *sc, uint16_t link_status)
657 struct usb_ether *ue = &sc->sc_ue;
663 if (sc->sc_flags & AXE_FLAG_772A) {
666 else if (sc->sc_flags & AXE_FLAG_772B) {
670 (void) axe_setmedium(sc);
676 if (sc->sc_flags & AXE_FLAG_772A)
678 else if (sc->sc_flags & AXE_FLAG_772B)
694 struct axe_softc *sc = device_get_softc(dev);
695 struct usb_ether *ue = &sc->sc_ue;
698 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
699 sc->sc_link_status = AXE_LINK_MASK;
703 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_RECURSE);
706 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
707 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
713 ue->ue_sc = sc;
716 ue->ue_mtx = &sc->sc_mtx;
733 struct axe_softc *sc = device_get_softc(dev);
734 struct usb_ether *ue = &sc->sc_ue;
736 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
738 mtx_destroy(&sc->sc_mtx);
750 struct axe_softc *sc = usbd_xfer_softc(xfer);
751 struct usb_ether *ue = &sc->sc_ue;
783 struct axe_softc *sc = ue->ue_sc;
792 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
801 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
816 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
830 sc->sc_lenmask) {
903 struct axe_softc *sc = usbd_xfer_softc(xfer);
905 struct usb_ether *ue = &(sc->sc_ue);
939 if (AXE_IS_178_FAMILY(sc)) {
987 struct axe_softc *sc = ue->ue_sc;
992 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
993 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1005 struct axe_softc *sc = uether_getsc(ue);
1012 AXE_LOCK_ASSERT(sc, MA_OWNED);
1018 axe_reset(sc);
1021 if (AXE_IS_178_FAMILY(sc)) {
1022 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
1023 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1024 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1026 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
1027 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1028 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1029 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1031 if (AXE_IS_178_FAMILY(sc)) {
1032 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1033 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1034 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1038 if (sc->sc_flags & AXE_FLAG_772B) {
1040 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1047 if (AXE_IS_178_FAMILY(sc)) {
1048 if (sc->sc_flags & AXE_FLAG_772B) {
1065 if (sc->sc_flags & AXE_FLAG_772A)
1079 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1084 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1085 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_RD]);
1094 struct axe_softc *sc = uether_getsc(ue);
1099 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1109 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1116 struct axe_softc *sc = uether_getsc(ue);
1119 AXE_LOCK_ASSERT(sc, MA_OWNED);
1121 link_status = axe_miibus_readreg(sc, MII_BMSR) & AXE_LINK_MASK;
1122 if (sc->sc_link_status != link_status) {
1123 axe_miibus_statchg(sc, link_status);
1124 sc->sc_link_status = link_status;
1131 struct axe_softc *sc = uether_getsc(ue);
1135 AXE_LOCK_ASSERT(sc, MA_OWNED);
1137 sc->sc_flags &= ~AXE_FLAG_LINK;
1141 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1142 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);