Lines Matching refs:b3
38 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
39 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
45 #define EMIT3_off32(b1, b2, b3, off) \
46 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
47 #define EMIT4_off32(b1, b2, b3, b4, off) \
48 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
628 u8 b1, b2, b3;
638 b3 = 0xC0;
639 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
651 b3 = 0xC0;
652 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
1062 u8 b2 = 0, b3 = 0;
1122 * b3 holds 'normal' opcode, b2 short form only valid
1127 b3 = 0xC0;
1131 b3 = 0xE8;
1135 b3 = 0xE0;
1139 b3 = 0xC8;
1143 b3 = 0xF0;
1149 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1153 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1273 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1275 EMIT2(0xD1, add_1reg(b3, dst_reg));
1277 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1326 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1327 EMIT2(0xD3, add_1reg(b3, dst_reg));