Lines Matching defs:par
167 struct tga_par *par = (struct tga_par *)info->par;
172 if (par->tga_type == TGA_TYPE_8PLANE) {
199 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8)
237 struct tga_par *par = (struct tga_par *) info->par;
238 int tga_bus_pci = dev_is_pci(par->dev);
239 int tga_bus_tc = TGA_BUS_TC(par->dev);
260 par->htimings = htimings;
261 par->vtimings = vtimings;
263 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
265 /* Store other useful values in par. */
266 par->xres = info->var.xres;
267 par->yres = info->var.yres;
268 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
269 par->bits_per_pixel = info->var.bits_per_pixel;
270 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
272 tga_type = par->tga_type;
275 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
278 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
281 TGA_WRITE_REG(par, deep_presets[tga_type] |
282 (par->sync_on_green ? 0x0 : 0x00010000),
284 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
289 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
290 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
291 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
294 tgafb_set_pll(par, pll_freq);
297 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
298 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
301 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
302 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
308 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
310 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
311 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
312 BT485_WRITE(par, 0x40, BT485_CMD_1);
313 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
314 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
317 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
318 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
321 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
323 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
325 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
327 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
334 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
335 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
336 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
337 (par->sync_on_green ? 0xc0 : 0x40));
339 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
342 BT459_LOAD_ADDR(par, 0x0000);
343 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
346 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
347 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
348 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
349 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
355 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
356 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
357 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
358 (par->sync_on_green ? 0xc0 : 0x40));
360 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
361 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
362 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
363 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
365 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
366 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
367 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
368 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
371 BT463_LOAD_ADDR(par, 0x0000);
372 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
378 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
379 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
380 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
386 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
387 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
388 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
389 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
393 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
395 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
397 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
399 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
401 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
402 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
405 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
406 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
407 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
413 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
430 tgafb_set_pll(struct tga_par *par, int f)
436 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
448 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
449 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
452 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
455 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
459 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
463 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
469 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
470 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
472 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
499 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
501 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
503 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
504 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
521 struct tga_par *par = (struct tga_par *) info->par;
522 int tga_bus_pci = dev_is_pci(par->dev);
523 int tga_bus_tc = TGA_BUS_TC(par->dev);
531 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
532 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
533 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
534 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
535 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
536 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
537 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
538 BT459_LOAD_ADDR(par, regno);
539 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
540 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
541 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
542 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
548 BT463_LOAD_ADDR(par, regno);
549 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
550 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
551 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
552 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
567 struct tga_par *par = (struct tga_par *) info->par;
573 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
574 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
575 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
580 if (par->vesa_blanked) {
581 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
582 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
583 par->vesa_blanked = 0;
585 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
589 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
594 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
595 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
596 par->vesa_blanked = 1;
600 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
601 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
602 par->vesa_blanked = 1;
606 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
607 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
608 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
609 par->vesa_blanked = 1;
625 struct tga_par *par = (struct tga_par *) info->par;
655 regs_base = par->tga_regs_base;
656 fb_base = par->tga_fb_base;
838 struct tga_par *par = (struct tga_par *) info->par;
861 regs_base = par->tga_regs_base;
862 fb_base = par->tga_fb_base;
925 struct tga_par *par = (struct tga_par *) info->par;
939 regs_base = par->tga_regs_base;
940 fb_base = par->tga_fb_base;
1058 struct tga_par *par = (struct tga_par *) info->par;
1059 void __iomem *tga_regs = par->tga_regs_base;
1103 struct tga_par *par = (struct tga_par *) info->par;
1104 void __iomem *tga_regs = par->tga_regs_base;
1105 void __iomem *tga_fb = par->tga_fb_base;
1153 struct tga_par *par = (struct tga_par *) info->par;
1201 tga_regs = par->tga_regs_base;
1202 tga_fb = par->tga_fb_base;
1316 struct tga_par *par = (struct tga_par *)info->par;
1317 int tga_bus_pci = dev_is_pci(par->dev);
1318 int tga_bus_tc = TGA_BUS_TC(par->dev);
1319 u8 tga_type = par->tga_type;
1359 info->fix.smem_start = (size_t) par->tga_fb_base;
1361 info->fix.mmio_start = (size_t) par->tga_regs_base;
1414 struct tga_par *par;
1424 /* Allocate the fb and par structures. */
1429 par = info->par;
1456 par->dev = dev;
1457 par->tga_mem_base = mem_base;
1458 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1459 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1460 par->tga_type = tga_type;
1462 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1464 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1470 info->screen_base = par->tga_fb_base;
1471 info->pseudo_palette = par->palette;
1511 par->tga_chip_rev);
1519 par->tga_chip_rev);
1542 struct tga_par *par;
1548 par = info->par;
1551 iounmap(par->tga_mem_base);