Lines Matching refs:pc
244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
246 return readl(pc->base + reg);
249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
252 writel(val, pc->base + reg);
255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
259 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
267 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
271 struct bcm2835_pinctrl *pc, unsigned pin)
273 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
276 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
283 struct bcm2835_pinctrl *pc, unsigned pin,
286 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
289 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
300 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
302 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
308 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
320 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
322 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
327 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
342 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
344 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
400 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
407 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
409 events &= pc->enabled_irq_map[bank];
412 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
420 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
440 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
443 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
444 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
447 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
459 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
464 value = bcm2835_gpio_rd(pc, reg);
469 bcm2835_gpio_wr(pc, reg, value);
473 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
476 switch (pc->irq_type[offset]) {
478 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
482 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
486 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
487 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
491 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
495 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
503 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
509 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
510 set_bit(offset, &pc->enabled_irq_map[bank]);
511 bcm2835_gpio_irq_config(pc, gpio, true);
512 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
518 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
524 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
525 bcm2835_gpio_irq_config(pc, gpio, false);
527 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
528 clear_bit(offset, &pc->enabled_irq_map[bank]);
529 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
532 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
542 pc->irq_type[offset] = type;
552 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
557 if (pc->irq_type[offset] != type) {
558 bcm2835_gpio_irq_config(pc, offset, false);
559 pc->irq_type[offset] = type;
564 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
566 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
567 bcm2835_gpio_irq_config(pc, offset, false);
568 pc->irq_type[offset] = type;
569 } else if (pc->irq_type[offset] != type) {
570 bcm2835_gpio_irq_config(pc, offset, false);
571 pc->irq_type[offset] = type;
572 bcm2835_gpio_irq_config(pc, offset, true);
577 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
579 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
580 bcm2835_gpio_irq_config(pc, offset, false);
581 pc->irq_type[offset] = type;
582 } else if (pc->irq_type[offset] != type) {
583 bcm2835_gpio_irq_config(pc, offset, false);
584 pc->irq_type[offset] = type;
585 bcm2835_gpio_irq_config(pc, offset, true);
590 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
592 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
593 bcm2835_gpio_irq_config(pc, offset, true);
594 pc->irq_type[offset] = type;
595 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
597 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
598 bcm2835_gpio_irq_config(pc, offset, true);
599 pc->irq_type[offset] = type;
600 } else if (pc->irq_type[offset] != type) {
601 bcm2835_gpio_irq_config(pc, offset, false);
602 pc->irq_type[offset] = type;
603 bcm2835_gpio_irq_config(pc, offset, true);
609 if (pc->irq_type[offset] != type) {
610 bcm2835_gpio_irq_config(pc, offset, false);
611 pc->irq_type[offset] = type;
612 bcm2835_gpio_irq_config(pc, offset, true);
625 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
632 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
634 if (test_bit(offset, &pc->enabled_irq_map[bank]))
635 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
637 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
644 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
652 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
655 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
661 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
666 if (!pc->wake_irq)
679 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
681 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
724 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
725 struct gpio_chip *chip = &pc->gpio_chip;
726 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
728 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
733 irq, irq_type_names[pc->irq_type[offset]]);
748 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
755 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
767 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
775 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
797 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
812 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
820 dev_err(pc->dev,
831 dev_err(pc->dev,
838 dev_err(pc->dev,
858 if (pin >= pc->pctl_desc.npins) {
859 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
870 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
880 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
909 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
912 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
943 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
945 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
954 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
957 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
965 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
969 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
991 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
999 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1007 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1009 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1016 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1027 bcm2835_pull_config_set(pc, pin, arg);
1032 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1036 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1040 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1045 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1063 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1073 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1076 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1083 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1101 bcm2711_pull_config_set(pc, pin, arg);
1106 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1109 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1112 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1117 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1203 struct bcm2835_pinctrl *pc;
1213 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1214 if (!pc)
1217 platform_set_drvdata(pdev, pc);
1218 pc->dev = dev;
1226 pc->base = devm_ioremap_resource(dev, &iomem);
1227 if (IS_ERR(pc->base))
1228 return PTR_ERR(pc->base);
1237 pc->gpio_chip = *pdata->gpio_chip;
1238 pc->gpio_chip.parent = dev;
1239 pc->gpio_chip.of_node = np;
1246 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1247 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1248 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1249 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1250 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1251 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1254 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1256 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1258 raw_spin_lock_init(&pc->irq_lock[i]);
1261 pc->pctl_desc = *pdata->pctl_desc;
1262 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1263 if (IS_ERR(pc->pctl_dev)) {
1264 gpiochip_remove(&pc->gpio_chip);
1265 return PTR_ERR(pc->pctl_dev);
1268 pc->gpio_range = *pdata->gpio_range;
1269 pc->gpio_range.base = pc->gpio_chip.base;
1270 pc->gpio_range.gc = &pc->gpio_chip;
1271 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1273 girq = &pc->gpio_chip.irq;
1286 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1287 sizeof(*pc->wake_irq),
1289 if (!pc->wake_irq) {
1311 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1314 len = strlen(dev_name(pc->dev)) + 16;
1315 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1321 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1324 err = devm_request_irq(dev, pc->wake_irq[i],
1326 IRQF_SHARED, name, pc);
1329 pc->wake_irq[i]);
1335 err = gpiochip_add_data(&pc->gpio_chip, pc);
1344 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);