Lines Matching defs:qphy
420 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
422 const struct qusb2_phy_cfg *cfg = qphy->cfg;
423 struct override_params *or = &qphy->overrides;
426 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
431 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
436 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
441 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
446 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
453 qusb2_setbits(qphy->base,
457 qusb2_clrbits(qphy->base,
463 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
473 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
475 struct device *dev = &qphy->phy->dev;
476 const struct qusb2_phy_cfg *cfg = qphy->cfg;
480 if (!qphy->cell)
490 val = nvmem_cell_read(qphy->cell, NULL);
504 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
507 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
514 struct qusb2_phy *qphy = phy_get_drvdata(phy);
516 qphy->mode = mode;
523 struct qusb2_phy *qphy = dev_get_drvdata(dev);
524 const struct qusb2_phy_cfg *cfg = qphy->cfg;
527 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
529 if (!qphy->phy_initialized) {
541 switch (qphy->mode) {
559 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
563 qusb2_setbits(qphy->base,
570 if (qphy->mode != PHY_MODE_INVALID) {
571 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
574 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
578 if (!qphy->has_se_clk_scheme)
579 clk_disable_unprepare(qphy->ref_clk);
581 clk_disable_unprepare(qphy->cfg_ahb_clk);
582 clk_disable_unprepare(qphy->iface_clk);
589 struct qusb2_phy *qphy = dev_get_drvdata(dev);
590 const struct qusb2_phy_cfg *cfg = qphy->cfg;
593 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
595 if (!qphy->phy_initialized) {
600 ret = clk_prepare_enable(qphy->iface_clk);
606 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
612 if (!qphy->has_se_clk_scheme) {
613 ret = clk_prepare_enable(qphy->ref_clk);
620 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
624 qusb2_clrbits(qphy->base,
632 clk_disable_unprepare(qphy->cfg_ahb_clk);
634 clk_disable_unprepare(qphy->iface_clk);
641 struct qusb2_phy *qphy = phy_get_drvdata(phy);
642 const struct qusb2_phy_cfg *cfg = qphy->cfg;
650 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
654 ret = clk_prepare_enable(qphy->iface_clk);
661 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
668 ret = reset_control_assert(qphy->phy_reset);
677 ret = reset_control_deassert(qphy->phy_reset);
684 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
685 qphy->cfg->disable_ctrl);
689 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
692 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
696 qusb2_phy_override_phy_params(qphy);
699 qusb2_phy_set_tune2_param(qphy);
702 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
709 qphy->has_se_clk_scheme = true;
716 if (qphy->tcsr) {
717 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
728 qphy->has_se_clk_scheme = false;
735 if (!qphy->has_se_clk_scheme) {
736 ret = clk_prepare_enable(qphy->ref_clk);
745 if (!qphy->has_se_clk_scheme)
750 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
753 readl(qphy->base + QUSB2PHY_PLL_TEST);
759 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
766 qphy->phy_initialized = true;
771 if (!qphy->has_se_clk_scheme)
772 clk_disable_unprepare(qphy->ref_clk);
774 reset_control_assert(qphy->phy_reset);
776 clk_disable_unprepare(qphy->cfg_ahb_clk);
778 clk_disable_unprepare(qphy->iface_clk);
780 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
787 struct qusb2_phy *qphy = phy_get_drvdata(phy);
790 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
791 qphy->cfg->disable_ctrl);
793 if (!qphy->has_se_clk_scheme)
794 clk_disable_unprepare(qphy->ref_clk);
796 reset_control_assert(qphy->phy_reset);
798 clk_disable_unprepare(qphy->cfg_ahb_clk);
799 clk_disable_unprepare(qphy->iface_clk);
801 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
803 qphy->phy_initialized = false;
848 struct qusb2_phy *qphy;
857 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
858 if (!qphy)
860 or = &qphy->overrides;
863 qphy->base = devm_ioremap_resource(dev, res);
864 if (IS_ERR(qphy->base))
865 return PTR_ERR(qphy->base);
867 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
868 if (IS_ERR(qphy->cfg_ahb_clk)) {
869 ret = PTR_ERR(qphy->cfg_ahb_clk);
875 qphy->ref_clk = devm_clk_get(dev, "ref");
876 if (IS_ERR(qphy->ref_clk)) {
877 ret = PTR_ERR(qphy->ref_clk);
883 qphy->iface_clk = devm_clk_get_optional(dev, "iface");
884 if (IS_ERR(qphy->iface_clk))
885 return PTR_ERR(qphy->iface_clk);
887 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
888 if (IS_ERR(qphy->phy_reset)) {
890 return PTR_ERR(qphy->phy_reset);
893 num = ARRAY_SIZE(qphy->vregs);
895 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
897 ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
906 qphy->cfg = of_device_get_match_data(dev);
908 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
910 if (IS_ERR(qphy->tcsr)) {
912 qphy->tcsr = NULL;
915 qphy->cell = devm_nvmem_cell_get(dev, NULL);
916 if (IS_ERR(qphy->cell)) {
917 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
919 qphy->cell = NULL;
980 qphy->phy = generic_phy;
982 dev_set_drvdata(dev, qphy);
983 phy_set_drvdata(generic_phy, qphy);