Lines Matching refs:val
146 int val;
148 val = phy_read_paged(phydev, priv->hw_stats[i].page,
150 if (val < 0)
153 val = val & priv->hw_stats[i].mask;
154 priv->stats[i] += val;
603 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
605 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
606 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
646 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
686 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
696 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
703 return __phy_package_write(phydev, regnum, val);
721 u32 val, val_l, val_h;
752 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
754 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
756 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
772 enum csr_target target, u32 reg, u32 val)
790 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
793 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
811 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
813 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
815 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
825 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
827 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
828 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
833 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
841 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
1146 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1155 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1411 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1420 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1486 u16 val, addr;
1494 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1506 if (val & PHY_ADDR_REVERSED) {
1527 u16 val;
1580 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1581 val &= ~MAC_CFG_MASK;
1583 val |= MAC_CFG_QSGMII;
1585 val |= MAC_CFG_SGMII;
1587 val |= MAC_CFG_RGMII;
1593 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1603 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1606 val |= PROC_CMD_QSGMII_MAC;
1608 val |= PROC_CMD_SGMII_MAC;
1610 ret = vsc8584_cmd(phydev, val);
1645 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1646 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1647 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1649 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1804 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1825 u32 val;
1836 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1838 if (val == 0xffffffff)
1841 } while (time_before(jiffies, deadline) && (val & op));
1843 if (val & op)
1866 u16 val;
1892 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1894 val &= ~MAC_CFG_MASK;
1895 val |= MAC_CFG_QSGMII;
1896 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);