Lines Matching refs:reg
26 .reg = MSCC_PHY_ERR_RX_CNT,
31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
46 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
55 .reg = MSCC_PHY_ERR_RX_CNT,
60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
75 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT,
85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT,
95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
149 priv->hw_stats[i].reg);
646 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
686 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
718 enum csr_target target, u32 reg)
745 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
772 enum csr_target target, u32 reg, u32 val)
804 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
898 u16 reg;
907 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
908 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
909 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
914 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
915 reg |= EN_PATCH_RAM_TRAP_ADDR(4);
916 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
920 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
921 reg &= ~MICRO_NSOFT_RESET;
922 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
928 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
929 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
930 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1004 u16 reg;
1010 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1011 if (reg != 0x3eb7) {
1016 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1017 if (reg != 0x4012) {
1022 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1023 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1028 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1030 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1112 u16 crc, reg;
1119 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1120 reg |= SMI_BROADCAST_WR_EN;
1121 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1139 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1140 reg |= TR_CLK_DISABLE;
1141 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1146 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1155 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1159 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1160 reg &= ~TR_CLK_DISABLE;
1161 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1166 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1167 reg &= ~SMI_BROADCAST_WR_EN;
1168 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1366 u16 crc, reg;
1372 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1373 reg |= SMI_BROADCAST_WR_EN;
1374 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1378 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1379 reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1380 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1395 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1396 reg |= TR_CLK_DISABLE;
1397 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1403 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1404 reg &= ~0x007f;
1405 reg |= 0x0019;
1406 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1411 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1420 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1424 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1425 reg &= ~TR_CLK_DISABLE;
1426 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1431 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1432 reg &= ~SMI_BROADCAST_WR_EN;
1433 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1779 u16 reg;
1791 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1792 reg |= SMI_BROADCAST_WR_EN;
1793 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1797 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1798 reg |= BIT(15);
1799 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1804 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1808 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1809 reg &= ~BIT(15);
1810 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1814 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1815 reg &= ~SMI_BROADCAST_WR_EN;
1816 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1821 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1828 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1836 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1850 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1852 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1856 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1858 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1867 u32 reg;
1962 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1964 if (reg == 0xffffffff) {
1969 } while (time_before(jiffies, deadline) && (reg & BIT(12)));
1971 if (reg & BIT(12)) {
1989 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1991 if (reg == 0xffffffff) {
1996 } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
1998 if (!(reg & BIT(8))) {