Lines Matching defs:phydev
110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
122 struct vsc8531_private *priv = phydev->priv;
130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
132 struct vsc8531_private *priv = phydev->priv;
143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
145 struct vsc8531_private *priv = phydev->priv;
148 val = phy_read_paged(phydev, priv->hw_stats[i].page,
159 static void vsc85xx_get_stats(struct phy_device *phydev,
162 struct vsc8531_private *priv = phydev->priv;
169 data[i] = vsc85xx_get_stat(phydev, i);
172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
179 mutex_lock(&phydev->lock);
180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
184 mutex_unlock(&phydev->lock);
189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
234 return genphy_restart_aneg(phydev);
237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
273 static int vsc85xx_wol_set(struct phy_device *phydev,
281 u8 *mac_addr = phydev->attached_dev->dev_addr;
283 mutex_lock(&phydev->lock);
284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
286 rc = phy_restore_page(phydev, rc, rc);
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
347 mutex_unlock(&phydev->lock);
352 static void vsc85xx_wol_get(struct phy_device *phydev,
361 mutex_lock(&phydev->lock);
362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
382 mutex_unlock(&phydev->lock);
386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
390 struct device *dev = &phydev->mdio.dev;
412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
416 struct vsc8531_private *priv = phydev->priv;
417 struct device *dev = &phydev->mdio.dev;
428 phydev_err(phydev, "DT %s invalid\n", led);
436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
452 struct vsc8531_private *priv = phydev->priv;
461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
475 mutex_lock(&phydev->lock);
476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
479 mutex_unlock(&phydev->lock);
484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
490 mutex_lock(&phydev->lock);
491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
515 rc = genphy_soft_reset(phydev);
518 mutex_unlock(&phydev->lock);
530 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl,
549 if (phy_interface_is_rgmii(phydev))
552 mutex_lock(&phydev->lock);
554 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
555 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
558 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
562 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
565 mutex_unlock(&phydev->lock);
570 static int vsc85xx_default_config(struct phy_device *phydev)
572 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
574 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL,
579 static int vsc85xx_get_tunable(struct phy_device *phydev,
584 return vsc85xx_downshift_get(phydev, (u8 *)data);
590 static int vsc85xx_set_tunable(struct phy_device *phydev,
596 return vsc85xx_downshift_set(phydev, *(u8 *)data);
603 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
605 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
606 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
607 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
610 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
622 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
635 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
640 mutex_lock(&phydev->lock);
641 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
646 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
649 oldpage = phy_restore_page(phydev, oldpage, oldpage);
650 mutex_unlock(&phydev->lock);
655 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
680 mutex_lock(&phydev->lock);
681 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
686 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
689 oldpage = phy_restore_page(phydev, oldpage, oldpage);
690 mutex_unlock(&phydev->lock);
695 /* phydev->bus->mdio_lock should be locked when using this function */
696 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
698 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
699 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
703 return __phy_package_write(phydev, regnum, val);
706 /* phydev->bus->mdio_lock should be locked when using this function */
707 static int phy_base_read(struct phy_device *phydev, u32 regnum)
709 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
710 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
714 return __phy_package_read(phydev, regnum);
717 static u32 vsc85xx_csr_read(struct phy_device *phydev,
723 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
733 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
743 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
752 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
760 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
763 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
765 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
771 static int vsc85xx_csr_write(struct phy_device *phydev,
776 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
786 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
790 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
793 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
802 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
811 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
818 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
825 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
827 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
828 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
829 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
833 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
838 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
841 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
845 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
850 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
862 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
867 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
879 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
885 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
887 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
889 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
895 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
900 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
904 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
907 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
909 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
911 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
912 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
914 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
916 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
918 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
920 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
922 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
924 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
928 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
930 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
932 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
938 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
943 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
945 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
946 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
949 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
953 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
955 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
958 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
964 static int vsc8584_patch_fw(struct phy_device *phydev,
969 ret = vsc8584_micro_assert_reset(phydev);
971 dev_err(&phydev->mdio.dev,
976 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
982 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
985 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
987 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
990 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
994 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
996 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1002 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1007 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1010 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1016 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1022 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1028 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1037 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1043 static int vsc8574_config_pre_init(struct phy_device *phydev)
1109 struct device *dev = &phydev->mdio.dev;
1116 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1119 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1121 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1123 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1130 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1132 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1134 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1135 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1136 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1137 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1139 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1141 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1143 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1146 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1148 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1150 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1152 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1155 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1157 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1159 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1161 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1163 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1166 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1168 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1178 ret = vsc8584_get_fw_crc(phydev,
1185 serdes_init = vsc8574_is_serdes_init(phydev);
1188 ret = vsc8584_micro_assert_reset(phydev);
1201 if (vsc8584_patch_fw(phydev, fw))
1207 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1210 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1211 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1212 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1215 vsc8584_micro_deassert_reset(phydev, false);
1220 ret = vsc8584_get_fw_crc(phydev,
1231 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1234 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1238 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1246 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev,
1251 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
1254 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat);
1258 static int vsc8584_mcb_rd_trig(struct phy_device *phydev,
1264 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1270 phydev, MACRO_CTRL, mcb_reg_addr);
1274 static int vsc8584_mcb_wr_trig(struct phy_device *phydev,
1281 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1287 phydev, MACRO_CTRL, mcb_reg_addr);
1291 static int vsc8584_pll5g_reset(struct phy_device *phydev)
1296 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1302 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1305 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1313 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1319 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1322 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1332 static int vsc8584_config_pre_init(struct phy_device *phydev)
1364 struct device *dev = &phydev->mdio.dev;
1369 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1372 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1374 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1376 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1378 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1380 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1387 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1389 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1391 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1393 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1395 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1397 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1399 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1401 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1403 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1406 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1408 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1411 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1413 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1415 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1417 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1420 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1422 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1424 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1426 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1428 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1431 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1433 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1443 ret = vsc8584_get_fw_crc(phydev,
1451 if (vsc8584_patch_fw(phydev, fw))
1456 vsc8584_micro_deassert_reset(phydev, false);
1459 ret = vsc8584_get_fw_crc(phydev,
1469 ret = vsc8584_micro_assert_reset(phydev);
1473 vsc8584_micro_deassert_reset(phydev, true);
1476 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1483 static void vsc8584_get_base_addr(struct phy_device *phydev)
1485 struct vsc8531_private *vsc8531 = phydev->priv;
1488 phy_lock_mdio_bus(phydev);
1489 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1491 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1494 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1496 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1497 phy_unlock_mdio_bus(phydev);
1503 vsc8531->ts_base_addr = phydev->mdio.addr;
1507 vsc8531->base_addr = phydev->mdio.addr + addr;
1513 vsc8531->base_addr = phydev->mdio.addr - addr;
1523 static int vsc8584_config_init(struct phy_device *phydev)
1525 struct vsc8531_private *vsc8531 = phydev->priv;
1529 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1531 phy_lock_mdio_bus(phydev);
1546 if (phy_package_init_once(phydev)) {
1551 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1553 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1558 ret = vsc8574_config_pre_init(phydev);
1564 ret = vsc8584_config_pre_init(phydev);
1575 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1580 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1582 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1584 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1586 } else if (phy_interface_is_rgmii(phydev)) {
1593 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1597 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1602 if (!phy_interface_is_rgmii(phydev)) {
1605 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1610 ret = vsc8584_cmd(phydev, val);
1618 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1627 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1635 phy_unlock_mdio_bus(phydev);
1637 ret = vsc8584_macsec_init(phydev);
1641 ret = vsc8584_ptp_init(phydev);
1645 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1649 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1653 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL,
1659 ret = genphy_soft_reset(phydev);
1664 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1672 phy_unlock_mdio_bus(phydev);
1676 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1681 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1688 ret = vsc8584_handle_ts_interrupt(phydev);
1693 vsc8584_handle_macsec_interrupt(phydev);
1696 phy_mac_interrupt(phydev);
1701 static int vsc85xx_config_init(struct phy_device *phydev)
1704 struct vsc8531_private *vsc8531 = phydev->priv;
1706 rc = vsc85xx_default_config(phydev);
1710 rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1714 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1718 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1721 rc = vsc8531_pre_init_seq_set(phydev);
1726 rc = vsc85xx_eee_init_seq_set(phydev);
1731 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1739 static int vsc8584_did_interrupt(struct phy_device *phydev)
1743 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1744 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1749 static int vsc8514_config_pre_init(struct phy_device *phydev)
1777 struct device *dev = &phydev->mdio.dev;
1782 ret = vsc8584_pll5g_reset(phydev);
1788 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1791 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1793 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1795 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1797 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1799 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1801 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1804 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1806 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1808 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1810 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1812 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1814 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1816 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1821 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1828 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1836 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1850 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1852 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1856 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1858 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1861 static int vsc8514_config_init(struct phy_device *phydev)
1863 struct vsc8531_private *vsc8531 = phydev->priv;
1869 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1871 phy_lock_mdio_bus(phydev);
1884 if (phy_package_init_once(phydev))
1885 vsc8514_config_pre_init(phydev);
1887 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1892 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1896 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1900 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1905 ret = vsc8584_cmd(phydev,
1913 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1915 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1917 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1922 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1924 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1933 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1944 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1950 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1955 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
1960 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1962 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1965 phy_unlock_mdio_bus(phydev);
1972 phy_unlock_mdio_bus(phydev);
1977 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1982 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1987 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1989 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1992 phy_unlock_mdio_bus(phydev);
1999 phy_unlock_mdio_bus(phydev);
2003 phy_unlock_mdio_bus(phydev);
2005 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2011 ret = genphy_soft_reset(phydev);
2017 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2025 phy_unlock_mdio_bus(phydev);
2029 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2033 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2034 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2039 static int vsc85xx_config_intr(struct phy_device *phydev)
2043 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2044 vsc8584_config_macsec_intr(phydev);
2045 vsc8584_config_ts_intr(phydev);
2047 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2050 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2053 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2059 static int vsc85xx_config_aneg(struct phy_device *phydev)
2063 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2067 return genphy_config_aneg(phydev);
2070 static int vsc85xx_read_status(struct phy_device *phydev)
2074 rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2078 return genphy_read_status(phydev);
2081 static int vsc8514_probe(struct phy_device *phydev)
2088 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2092 phydev->priv = vsc8531;
2094 vsc8584_get_base_addr(phydev);
2095 devm_phy_package_join(&phydev->mdio.dev, phydev,
2102 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2107 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2110 static int vsc8574_probe(struct phy_device *phydev)
2117 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2121 phydev->priv = vsc8531;
2123 vsc8584_get_base_addr(phydev);
2124 devm_phy_package_join(&phydev->mdio.dev, phydev,
2131 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2136 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2139 static int vsc8584_probe(struct phy_device *phydev)
2147 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2148 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2152 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2156 phydev->priv = vsc8531;
2158 vsc8584_get_base_addr(phydev);
2159 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2166 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2171 if (phy_package_probe_once(phydev)) {
2172 ret = vsc8584_ptp_probe_once(phydev);
2177 ret = vsc8584_ptp_probe(phydev);
2181 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2184 static int vsc85xx_probe(struct phy_device *phydev)
2191 rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2195 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2199 phydev->priv = vsc8531;
2206 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2211 return vsc85xx_dt_led_modes_get(phydev, default_mode);