Lines Matching refs:ispi
22 /* Offsets are from @ispi->base */
60 /* Offset is from @ispi->pregs */
68 /* Offsets are from @ispi->sregs */
164 static void intel_spi_dump_regs(struct intel_spi *ispi)
169 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
171 value = readl(ispi->base + HSFSTS_CTL);
172 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
174 dev_dbg(ispi->dev, "-> Locked\n");
176 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
177 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
180 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
181 i, readl(ispi->base + FDATA(i)));
183 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
185 for (i = 0; i < ispi->nregions; i++)
186 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
187 readl(ispi->base + FREG(i)));
188 for (i = 0; i < ispi->pr_num; i++)
189 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
190 readl(ispi->pregs + PR(i)));
192 if (ispi->sregs) {
193 value = readl(ispi->sregs + SSFSTS_CTL);
194 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
195 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
196 readl(ispi->sregs + PREOP_OPTYPE));
197 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
198 readl(ispi->sregs + OPMENU0));
199 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
200 readl(ispi->sregs + OPMENU1));
203 if (ispi->info->type == INTEL_SPI_BYT)
204 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
206 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
207 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
209 dev_dbg(ispi->dev, "Protected regions:\n");
210 for (i = 0; i < ispi->pr_num; i++) {
213 value = readl(ispi->pregs + PR(i));
220 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
226 dev_dbg(ispi->dev, "Flash regions:\n");
227 for (i = 0; i < ispi->nregions; i++) {
230 region = readl(ispi->base + FREG(i));
235 dev_dbg(ispi->dev, " %02d disabled\n", i);
237 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
241 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
242 ispi->swseq_reg ? 'S' : 'H');
243 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
244 ispi->swseq_erase ? 'S' : 'H');
248 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
258 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
268 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
279 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
288 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
292 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
297 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
301 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
306 static bool intel_spi_set_writeable(struct intel_spi *ispi)
308 if (!ispi->info->set_writeable)
311 return ispi->info->set_writeable(ispi->base, ispi->info->data);
314 static int intel_spi_init(struct intel_spi *ispi)
319 switch (ispi->info->type) {
321 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
322 ispi->pregs = ispi->base + BYT_PR;
323 ispi->nregions = BYT_FREG_NUM;
324 ispi->pr_num = BYT_PR_NUM;
325 ispi->swseq_reg = true;
329 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
330 ispi->pregs = ispi->base + LPT_PR;
331 ispi->nregions = LPT_FREG_NUM;
332 ispi->pr_num = LPT_PR_NUM;
333 ispi->swseq_reg = true;
337 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
338 ispi->pregs = ispi->base + BXT_PR;
339 ispi->nregions = BXT_FREG_NUM;
340 ispi->pr_num = BXT_PR_NUM;
341 ispi->erase_64k = true;
345 ispi->sregs = NULL;
346 ispi->pregs = ispi->base + CNL_PR;
347 ispi->nregions = CNL_FREG_NUM;
348 ispi->pr_num = CNL_PR_NUM;
356 if (writeable && !intel_spi_set_writeable(ispi)) {
357 dev_warn(ispi->dev, "can't disable chip write protection\n");
362 val = readl(ispi->base + HSFSTS_CTL);
364 writel(val, ispi->base + HSFSTS_CTL);
374 lvscc = readl(ispi->base + LVSCC);
375 uvscc = readl(ispi->base + UVSCC);
377 ispi->swseq_erase = true;
379 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
382 ispi->erase_64k = false;
384 if (ispi->sregs == NULL && (ispi->swseq_reg || ispi->swseq_erase)) {
385 dev_err(ispi->dev, "software sequencer not supported, but required\n");
394 if (ispi->swseq_reg) {
396 val = readl(ispi->sregs + SSFSTS_CTL);
398 writel(val, ispi->sregs + SSFSTS_CTL);
402 val = readl(ispi->base + HSFSTS_CTL);
403 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
405 if (ispi->locked && ispi->sregs) {
411 opmenu0 = readl(ispi->sregs + OPMENU0);
412 opmenu1 = readl(ispi->sregs + OPMENU1);
415 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
416 ispi->opcodes[i] = opmenu0 >> i * 8;
417 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
422 intel_spi_dump_regs(ispi);
427 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
432 if (ispi->locked) {
433 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
434 if (ispi->opcodes[i] == opcode)
441 writel(opcode, ispi->sregs + OPMENU0);
442 preop = readw(ispi->sregs + PREOP_OPTYPE);
443 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
448 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
453 val = readl(ispi->base + HSFSTS_CTL);
476 writel(val, ispi->base + HSFSTS_CTL);
478 ret = intel_spi_wait_hw_busy(ispi);
482 status = readl(ispi->base + HSFSTS_CTL);
491 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
498 ret = intel_spi_opcode_index(ispi, opcode, optype);
509 atomic_preopcode = ispi->atomic_preopcode;
510 ispi->atomic_preopcode = 0;
525 preop = readw(ispi->sregs + PREOP_OPTYPE);
542 writel(val, ispi->sregs + SSFSTS_CTL);
544 ret = intel_spi_wait_sw_busy(ispi);
548 status = readl(ispi->sregs + SSFSTS_CTL);
560 struct intel_spi *ispi = nor->priv;
564 writel(0, ispi->base + FADDR);
566 if (ispi->swseq_reg)
567 ret = intel_spi_sw_cycle(ispi, opcode, len,
570 ret = intel_spi_hw_cycle(ispi, opcode, len);
575 return intel_spi_read_block(ispi, buf, len);
581 struct intel_spi *ispi = nor->priv;
596 if (!ispi->swseq_reg)
599 preop = readw(ispi->sregs + PREOP_OPTYPE);
601 if (ispi->locked)
603 writel(opcode, ispi->sregs + PREOP_OPTYPE);
610 ispi->atomic_preopcode = opcode;
623 writel(0, ispi->base + FADDR);
626 ret = intel_spi_write_block(ispi, buf, len);
630 if (ispi->swseq_reg)
631 return intel_spi_sw_cycle(ispi, opcode, len,
633 return intel_spi_hw_cycle(ispi, opcode, len);
639 struct intel_spi *ispi = nor->priv;
648 if (WARN_ON_ONCE(ispi->atomic_preopcode))
649 ispi->atomic_preopcode = 0;
668 writel(from, ispi->base + FADDR);
670 val = readl(ispi->base + HSFSTS_CTL);
676 writel(val, ispi->base + HSFSTS_CTL);
678 ret = intel_spi_wait_hw_busy(ispi);
682 status = readl(ispi->base + HSFSTS_CTL);
689 dev_err(ispi->dev, "read error: %llx: %#x\n", from,
694 ret = intel_spi_read_block(ispi, read_buf, block_size);
710 struct intel_spi *ispi = nor->priv;
716 ispi->atomic_preopcode = 0;
725 writel(to, ispi->base + FADDR);
727 val = readl(ispi->base + HSFSTS_CTL);
733 ret = intel_spi_write_block(ispi, write_buf, block_size);
735 dev_err(ispi->dev, "failed to write block\n");
741 writel(val, ispi->base + HSFSTS_CTL);
743 ret = intel_spi_wait_hw_busy(ispi);
745 dev_err(ispi->dev, "timeout\n");
749 status = readl(ispi->base + HSFSTS_CTL);
756 dev_err(ispi->dev, "write error: %llx: %#x\n", to,
773 struct intel_spi *ispi = nor->priv;
778 if (len >= SZ_64K && ispi->erase_64k) {
786 if (ispi->swseq_erase) {
788 writel(offs, ispi->base + FADDR);
790 ret = intel_spi_sw_cycle(ispi, nor->erase_opcode,
803 ispi->atomic_preopcode = 0;
806 writel(offs, ispi->base + FADDR);
808 val = readl(ispi->base + HSFSTS_CTL);
813 writel(val, ispi->base + HSFSTS_CTL);
815 ret = intel_spi_wait_hw_busy(ispi);
819 status = readl(ispi->base + HSFSTS_CTL);
832 static bool intel_spi_is_protected(const struct intel_spi *ispi,
837 for (i = 0; i < ispi->pr_num; i++) {
840 pr_value = readl(ispi->pregs + PR(i));
858 static void intel_spi_fill_partition(struct intel_spi *ispi,
874 for (i = 1; i < ispi->nregions; i++) {
877 region = readl(ispi->base + FREG(i));
891 if (!writeable || intel_spi_is_protected(ispi, base, limit))
917 struct intel_spi *ispi;
923 ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
924 if (!ispi)
927 ispi->base = devm_ioremap_resource(dev, mem);
928 if (IS_ERR(ispi->base))
929 return ERR_CAST(ispi->base);
931 ispi->dev = dev;
932 ispi->info = info;
934 ret = intel_spi_init(ispi);
938 ispi->nor.dev = ispi->dev;
939 ispi->nor.priv = ispi;
940 ispi->nor.controller_ops = &intel_spi_controller_ops;
942 ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
948 intel_spi_fill_partition(ispi, &part);
950 ret = mtd_device_register(&ispi->nor.mtd, &part, 1);
954 return ispi;
958 int intel_spi_remove(struct intel_spi *ispi)
960 return mtd_device_unregister(&ispi->nor.mtd);