Lines Matching refs:sdr
1136 const struct nand_sdr_timings *sdr =
1184 PSEC_TO_MSEC(sdr->tPROG_max));
1616 const struct nand_sdr_timings *sdr =
1655 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
2378 const struct nand_sdr_timings *sdr;
2382 sdr = nand_get_sdr_timings(conf);
2383 if (IS_ERR(sdr))
2384 return PTR_ERR(sdr);
2397 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
2399 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
2401 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
2402 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
2403 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
2410 read_delay = sdr->tRC_min >= 30000 ?
2413 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
2419 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
2421 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
2429 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
2431 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,