Lines Matching refs:NDCR
123 #define NDCR 0x00
513 reg = readl_relaxed(nfc->regs + NDCR);
514 writel_relaxed(reg | int_mask, nfc->regs + NDCR);
522 reg = readl_relaxed(nfc->regs + NDCR);
523 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
551 ndcr = readl_relaxed(nfc->regs + NDCR);
558 writel_relaxed(ndcr, nfc->regs + NDCR);
571 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
576 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
577 nfc->regs + NDCR);
612 ndcr = readl_relaxed(nfc->regs + NDCR);
616 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
639 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
681 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
763 * Reset the NDCR register to a clean state for this particular chip,
766 ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
768 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
787 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
790 * RDY interrupt mask is one bit in NDCR while there are two status
811 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
814 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
828 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
831 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
842 reg = readl_relaxed(nfc->regs + NDCR);
843 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
850 reg = readl_relaxed(nfc->regs + NDCR);
851 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
1866 * NDCR ND_RUN bit should be cleared automatically at the end of each
1873 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1874 nfc->regs + NDCR);
1938 * NDCR ND_RUN bit should be cleared automatically at the end of each
1945 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1946 nfc->regs + NDCR);
2497 /* Save the chip-specific fields of NDCR */
2883 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);