Lines Matching defs:ret
565 int ret;
571 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
574 if (ret) {
578 return ret;
603 int ret;
606 ret = marvell_nfc_wait_ndrun(chip);
607 if (ret) {
609 return ret;
617 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
620 if (ret) {
663 int ret;
665 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
669 if (ret) {
674 return ret;
723 int ret;
730 ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0),
737 ret = wait_for_completion_timeout(&nfc->complete,
747 if (!ret && !pending) {
863 int ret;
880 ret = dma_submit_error(cookie);
881 if (ret)
885 ret = marvell_nfc_wait_cmdd(nfc->selected_chip);
888 if (ret) {
1037 int ret;
1043 ret = marvell_nfc_prepare_cmd(chip);
1044 if (ret)
1045 return ret;
1048 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1050 if (ret)
1051 return ret;
1069 ret = marvell_nfc_wait_cmdd(chip);
1070 return ret;
1086 int max_bitflips = 0, ret;
1093 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
1096 if (!ret)
1152 int ret;
1158 ret = marvell_nfc_prepare_cmd(chip);
1159 if (ret)
1160 return ret;
1163 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1165 if (ret)
1166 return ret;
1179 ret = marvell_nfc_wait_cmdd(chip);
1180 if (ret)
1181 return ret;
1183 ret = marvell_nfc_wait_op(chip,
1185 if (ret)
1186 return ret;
1189 ret = nand_status_op(chip, &status);
1190 if (ret)
1191 return ret;
1212 int ret;
1216 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1220 return ret;
1297 int i, ret;
1307 ret = marvell_nfc_prepare_cmd(chip);
1308 if (ret)
1366 int chunk, ret;
1390 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
1391 if (ret)
1560 int ret;
1595 ret = marvell_nfc_prepare_cmd(chip);
1596 if (ret)
1597 return ret;
1600 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1602 if (ret)
1603 return ret;
1624 int chunk, ret;
1655 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
1659 if (ret)
1660 return ret;
1663 ret = nand_status_op(chip, &status);
1664 if (ret)
1665 return ret;
1795 int ret;
1803 ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
1807 ret = marvell_nfc_xfer_data_out_pio(nfc, out, len);
1813 return ret;
1821 int ret;
1826 ret = marvell_nfc_prepare_cmd(chip);
1827 if (ret)
1828 return ret;
1831 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1833 if (ret)
1834 return ret;
1840 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1841 if (ret)
1842 return ret;
1849 ret = marvell_nfc_wait_cmdd(chip);
1850 if (ret)
1851 return ret;
1857 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1858 if (ret)
1859 return ret;
1884 int ret;
1915 ret = marvell_nfc_prepare_cmd(chip);
1916 if (ret)
1917 return ret;
1922 ret = marvell_nfc_wait_cmdd(chip);
1924 return ret;
1927 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1929 if (ret)
1930 return ret;
1933 ret = marvell_nfc_wait_cmdd(chip);
1934 if (ret)
1935 return ret;
1956 int ret;
1960 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1963 return ret;
1970 int ret;
1976 ret = marvell_nfc_prepare_cmd(chip);
1977 if (ret)
1978 return ret;
1981 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1983 if (ret)
1984 return ret;
1989 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1990 if (ret)
1991 return ret;
1997 ret = marvell_nfc_wait_cmdd(chip);
1998 if (ret)
1999 return ret;
2010 int ret;
2016 ret = marvell_nfc_prepare_cmd(chip);
2017 if (ret)
2018 return ret;
2021 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
2023 if (ret)
2024 return ret;
2029 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2030 if (ret)
2031 return ret;
2037 ret = marvell_nfc_wait_cmdd(chip);
2038 if (ret)
2039 return ret;
2050 int ret;
2055 ret = marvell_nfc_prepare_cmd(chip);
2056 if (ret)
2057 return ret;
2060 ret = marvell_nfc_wait_cmdd(chip);
2061 if (ret)
2062 return ret;
2066 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2067 if (ret)
2068 return ret;
2079 int ret;
2084 ret = marvell_nfc_prepare_cmd(chip);
2085 if (ret)
2086 return ret;
2089 ret = marvell_nfc_wait_cmdd(chip);
2090 if (ret)
2091 return ret;
2095 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2096 if (ret)
2097 return ret;
2311 int ret;
2328 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
2329 if (ret)
2330 return ret;
2482 int ret;
2531 ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2532 if (ret) {
2533 dev_err(nfc->dev, "ECC init failed: %d\n", ret);
2534 return ret;
2590 int nsels, ret, i;
2633 ret = of_property_read_u32_index(np, "reg", i, &cs);
2634 if (ret) {
2636 ret);
2637 return ret;
2679 ret = of_property_read_u32_index(np, "nand-rb", i,
2681 if (ret) {
2684 ret);
2685 return ret;
2723 ret = nand_scan(chip, marvell_nand->nsels);
2724 if (ret) {
2726 return ret;
2731 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2733 ret = mtd_device_register(mtd, NULL, 0);
2734 if (ret) {
2735 dev_err(dev, "failed to register mtd device: %d\n", ret);
2737 return ret;
2749 int ret;
2753 ret = mtd_device_unregister(nand_to_mtd(chip));
2754 WARN_ON(ret);
2766 int ret;
2786 ret = marvell_nand_chip_init(dev, nfc, np);
2787 return ret;
2791 ret = marvell_nand_chip_init(dev, nfc, nand_np);
2792 if (ret) {
2803 return ret;
2813 int ret;
2821 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32));
2822 if (ret)
2823 return ret;
2827 ret = PTR_ERR(nfc->dma_chan);
2829 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n");
2834 ret = -ENXIO;
2844 ret = dmaengine_slave_config(nfc->dma_chan, &config);
2845 if (ret < 0) {
2858 ret = -ENOMEM;
2870 return ret;
2930 int ret;
2960 ret = clk_prepare_enable(nfc->core_clk);
2961 if (ret)
2962 return ret;
2967 ret = PTR_ERR(nfc->reg_clk);
2974 ret = clk_prepare_enable(nfc->reg_clk);
2975 if (ret)
2980 ret = devm_request_irq(dev, irq, marvell_nfc_isr,
2982 if (ret)
2993 ret = -EINVAL;
2998 ret = marvell_nfc_init(nfc);
2999 if (ret)
3004 ret = marvell_nand_chips_init(dev, nfc);
3005 if (ret)
3018 return ret;
3055 int ret;
3057 ret = clk_prepare_enable(nfc->core_clk);
3058 if (ret < 0)
3059 return ret;
3061 ret = clk_prepare_enable(nfc->reg_clk);
3062 if (ret < 0) {
3064 return ret;