Lines Matching defs:page
25 * there are at most 2 bitflips. Here is the page layout used by the
35 * not align with the page (data + OOB) size. ECC bytes are always
36 * 30B per ECC chunk. Here is the page layout used by the controller
238 * @writesize: Full page size on which the layout applies
950 * check if the entire page (with ECC bytes) is actually blank or not.
1022 bool raw, int page)
1033 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1034 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1054 * Read the page then the OOB area. Unlike what is shown in current
1074 int oob_required, int page)
1078 true, page);
1082 int oob_required, int page)
1092 page);
1100 * When ECC failures are detected, check if the full page has been
1108 lt->data_bytes, true, page);
1121 static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page)
1127 true, page);
1134 int page)
1147 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1148 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1168 /* Write the page then the OOB area */
1201 int oob_required, int page)
1205 true, page);
1210 int oob_required, int page)
1217 false, page);
1229 int page)
1238 true, page);
1243 int oob_required, int page)
1261 nand_read_page_op(chip, page, 0, NULL, 0);
1292 int page)
1302 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1303 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1358 int page)
1389 spare, spare_len, page);
1408 * user should re-read the page in raw mode if ECC bytes are required.
1413 * bytes in raw mode and check if the whole page is empty. In this case,
1417 * 2k page, 8b strength per 512B chunk), the controller tries to correct
1419 * this strange behavior, the whole page is re-read in raw mode, not
1457 * case, re-read the entire page.
1482 static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
1486 return chip->ecc.read_page_raw(chip, buf, true, page);
1489 static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page)
1493 return chip->ecc.read_page(chip, buf, true, page);
1499 int oob_required, int page)
1513 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1554 int page)
1583 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
1584 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
1614 int oob_required, int page)
1642 spare, spare_len, page);
1674 int page)
1681 return chip->ecc.write_page_raw(chip, buf, true, page);
1684 static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
1691 return chip->ecc.write_page(chip, buf, true, page);
2212 * 4KB page / 4bit BCH combination.
2259 "ECC strength %d at page size %d is not supported\n",
2503 * On small page NANDs, only one cycle is needed to pass the
2880 * offset in the read page and this will fail the protection.