Lines Matching defs:ecc
235 * a particular layout mixing data/spare/ecc is defined, with a possible last
248 * @ecc_bytes: Number of ecc bytes per chunk
251 * @last_ecc_bytes: Number of ecc bytes in the last chunk
820 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
832 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
941 u8 *ecc, int ecc_len,
956 if (!ecc)
959 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
960 spare, spare_len, chip->ecc.strength);
1006 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
1472 /* Check the entire chunk (data + spare + ecc) for emptyness */
1486 return chip->ecc.read_page_raw(chip, buf, true, page);
1493 return chip->ecc.read_page(chip, buf, true, page);
1681 return chip->ecc.write_page_raw(chip, buf, true, page);
1691 return chip->ecc.write_page(chip, buf, true, page);
2226 .ecc = marvell_nand_ooblayout_ecc,
2231 struct nand_ecc_ctrl *ecc)
2250 ecc->size == l->chunk && ecc->strength == l->strength) {
2257 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
2260 ecc->strength, mtd->writesize);
2275 ecc->steps = l->nchunks;
2276 ecc->size = l->data_bytes;
2278 if (ecc->strength == 1) {
2279 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2280 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
2281 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
2282 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
2283 ecc->read_oob = ecc->read_oob_raw;
2284 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
2285 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
2286 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
2287 ecc->write_oob = ecc->write_oob_raw;
2289 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2290 ecc->strength = 16;
2291 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
2292 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
2293 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
2294 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
2295 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
2296 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
2297 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
2298 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
2305 struct nand_ecc_ctrl *ecc)
2313 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2314 (!ecc->size || !ecc->strength)) {
2316 ecc->size = requirements->step_size;
2317 ecc->strength = requirements->strength;
2321 ecc->size = 512;
2322 ecc->strength = 1;
2326 switch (ecc->engine_type) {
2328 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
2527 chip->ecc.size = pdata->ecc_step_size;
2528 chip->ecc.strength = pdata->ecc_strength;
2531 ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2537 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
2709 * Default to HW ECC engine mode. If the nand-ecc-mode property is given
2712 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;