Lines Matching refs:nfc
205 static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)
210 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
214 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);
218 writel_relaxed(event, nfc->base + INTR_STS_REG);
223 static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,
231 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
235 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",
236 readl_relaxed(nfc->base + READY_STS_REG));
243 static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
245 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
246 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
247 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
248 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
249 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
278 struct arasan_nfc *nfc = to_anfc(chip->controller);
282 writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG);
285 if (nfc->cur_clk != anand->clk) {
286 clk_disable_unprepare(nfc->bus_clk);
287 ret = clk_set_rate(nfc->bus_clk, anand->clk);
289 dev_err(nfc->dev, "Failed to change clock rate\n");
293 ret = clk_prepare_enable(nfc->bus_clk);
295 dev_err(nfc->dev,
300 nfc->cur_clk = anand->clk;
331 struct arasan_nfc *nfc = to_anfc(chip->controller);
359 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE);
360 if (dma_mapping_error(nfc->dev, dma_addr)) {
361 dev_err(nfc->dev, "Buffer mapping error");
365 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
366 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
368 anfc_trigger_op(nfc, &nfc_op);
370 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
371 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE);
373 dev_err(nfc->dev, "Error reading page %d\n", page);
450 struct arasan_nfc *nfc = to_anfc(chip->controller);
478 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
481 nfc->base + ECC_SP_REG);
483 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE);
484 if (dma_mapping_error(nfc->dev, dma_addr)) {
485 dev_err(nfc->dev, "Buffer mapping error");
489 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
490 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
492 anfc_trigger_op(nfc, &nfc_op);
493 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
494 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE);
496 dev_err(nfc->dev, "Error writing page %d\n", page);
615 static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
625 ret = anfc_wait_for_event(nfc, dir);
627 dev_err(nfc->dev, "PIO %s ready signal not received\n",
634 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
637 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
647 remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
651 writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
655 return anfc_wait_for_event(nfc, XFER_COMPLETE);
662 struct arasan_nfc *nfc = to_anfc(chip->controller);
671 anfc_trigger_op(nfc, &nfc_op);
674 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
679 return anfc_rw_pio_op(nfc, &nfc_op);
710 struct arasan_nfc *nfc = to_anfc(chip->controller);
719 anfc_trigger_op(nfc, &nfc_op);
721 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
726 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
734 struct arasan_nfc *nfc = to_anfc(chip->controller);
746 tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
767 struct arasan_nfc *nfc = to_anfc(chip->controller);
775 return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
897 struct arasan_nfc *nfc = to_anfc(chip->controller);
898 struct device_node *np = nfc->dev->of_node;
1001 static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
1018 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize);
1040 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength);
1054 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength);
1070 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength,
1075 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL);
1093 struct arasan_nfc *nfc = to_anfc(chip->controller);
1140 ret = anfc_init_hw_ecc_controller(nfc, chip);
1143 dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
1166 static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)
1173 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);
1179 dev_err(nfc->dev, "Invalid reg property\n");
1192 dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb);
1196 if (test_and_set_bit(cs, &nfc->assigned_cs)) {
1197 dev_err(nfc->dev, "Already assigned CS %d\n", cs);
1206 mtd->dev.parent = nfc->dev;
1207 chip->controller = &nfc->controller;
1213 dev_err(nfc->dev, "NAND label property is mandatory\n");
1219 dev_err(nfc->dev, "Scan operation failed\n");
1229 list_add_tail(&anand->node, &nfc->chips);
1234 static void anfc_chips_cleanup(struct arasan_nfc *nfc)
1240 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {
1249 static int anfc_chips_init(struct arasan_nfc *nfc)
1251 struct device_node *np = nfc->dev->of_node, *nand_np;
1256 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
1262 ret = anfc_chip_init(nfc, nand_np);
1265 anfc_chips_cleanup(nfc);
1273 static void anfc_reset(struct arasan_nfc *nfc)
1276 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
1279 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
1284 struct arasan_nfc *nfc;
1287 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
1288 if (!nfc)
1291 nfc->dev = &pdev->dev;
1292 nand_controller_init(&nfc->controller);
1293 nfc->controller.ops = &anfc_ops;
1294 INIT_LIST_HEAD(&nfc->chips);
1296 nfc->base = devm_platform_ioremap_resource(pdev, 0);
1297 if (IS_ERR(nfc->base))
1298 return PTR_ERR(nfc->base);
1300 anfc_reset(nfc);
1302 nfc->controller_clk = devm_clk_get(&pdev->dev, "controller");
1303 if (IS_ERR(nfc->controller_clk))
1304 return PTR_ERR(nfc->controller_clk);
1306 nfc->bus_clk = devm_clk_get(&pdev->dev, "bus");
1307 if (IS_ERR(nfc->bus_clk))
1308 return PTR_ERR(nfc->bus_clk);
1310 ret = clk_prepare_enable(nfc->controller_clk);
1314 ret = clk_prepare_enable(nfc->bus_clk);
1318 ret = anfc_chips_init(nfc);
1322 platform_set_drvdata(pdev, nfc);
1327 clk_disable_unprepare(nfc->bus_clk);
1330 clk_disable_unprepare(nfc->controller_clk);
1337 struct arasan_nfc *nfc = platform_get_drvdata(pdev);
1339 anfc_chips_cleanup(nfc);
1341 clk_disable_unprepare(nfc->bus_clk);
1342 clk_disable_unprepare(nfc->controller_clk);
1352 .compatible = "arasan,nfc-v3p10",