Lines Matching refs:cr2
185 * @cr2: Control register 2
192 u32 cr2;
769 u32 cr2;
774 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
776 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
778 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
780 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
781 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
784 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
790 u32 cr2;
804 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
805 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
806 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
807 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
852 u32 cr1, cr2;
864 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
867 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
869 cr2 |= STM32F7_I2C_CR2_RD_WRN;
872 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
874 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
875 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
876 cr2 |= STM32F7_I2C_CR2_ADD10;
878 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
879 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
883 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
885 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
886 cr2 |= STM32F7_I2C_CR2_RELOAD;
888 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
926 cr2 |= STM32F7_I2C_CR2_START;
932 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
942 u32 cr1, cr2;
948 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
952 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
954 cr2 |= STM32F7_I2C_CR2_RD_WRN;
957 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
958 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
974 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
985 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
997 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1016 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1029 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1046 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1051 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1055 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1056 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1070 cr2 & STM32F7_I2C_CR2_RD_WRN,
1081 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1086 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1093 cr2 |= STM32F7_I2C_CR2_START;
1099 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1108 u32 cr1, cr2;
1111 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1115 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1128 cr2 |= STM32F7_I2C_CR2_RELOAD;
1137 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1142 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1143 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1164 cr2 & STM32F7_I2C_CR2_RD_WRN,
1181 cr2 |= STM32F7_I2C_CR2_START;
1185 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1402 u32 cr2, status, mask;
1429 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1430 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1431 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
2313 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2345 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);