Lines Matching defs:i2c_dev
410 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
412 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
427 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
451 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
458 dev_err(i2c_dev->dev,
466 dev_err(i2c_dev->dev,
494 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
535 dev_err(i2c_dev->dev, "no Prescaler solution\n");
592 dev_err(i2c_dev->dev, "no solution at all\n");
603 dev_dbg(i2c_dev->dev,
630 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
637 t->scl_rise_ns = i2c_dev->setup.rise_time;
638 t->scl_fall_ns = i2c_dev->setup.fall_time;
640 i2c_parse_fw_timings(i2c_dev->dev, t, false);
643 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
649 i2c_dev->setup.rise_time = t->scl_rise_ns;
650 i2c_dev->setup.fall_time = t->scl_fall_ns;
651 setup->clock_src = clk_get_rate(i2c_dev->clk);
654 dev_err(i2c_dev->dev, "clock rate is 0\n");
659 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
660 &i2c_dev->timing);
662 dev_err(i2c_dev->dev,
668 dev_warn(i2c_dev->dev,
675 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
679 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
681 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
683 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
686 i2c_dev->bus_rate = setup->speed_freq;
691 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
693 void __iomem *base = i2c_dev->base;
701 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
702 struct stm32_i2c_dma *dma = i2c_dev->dma;
705 stm32f7_i2c_disable_dma_req(i2c_dev);
710 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
712 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
721 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
724 if (i2c_dev->setup.analog_filter)
725 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
728 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
732 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
734 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
735 STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
737 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
741 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
743 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
744 void __iomem *base = i2c_dev->base;
752 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
754 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
755 void __iomem *base = i2c_dev->base;
766 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
768 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
771 if (i2c_dev->use_dma)
774 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
784 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
787 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
797 stm32f7_i2c_read_rx_data(i2c_dev);
804 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
807 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
812 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
814 dev_info(i2c_dev->dev, "Trying to recover bus\n");
816 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
819 stm32f7_i2c_hw_config(i2c_dev);
824 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
829 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
836 dev_info(i2c_dev->dev, "bus busy\n");
838 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
840 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
847 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
850 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
851 void __iomem *base = i2c_dev->base;
859 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
861 reinit_completion(&i2c_dev->complete);
900 i2c_dev->use_dma = false;
901 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
902 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
906 i2c_dev);
908 i2c_dev->use_dma = true;
910 dev_warn(i2c_dev->dev, "can't use DMA\n");
913 if (!i2c_dev->use_dma) {
928 i2c_dev->master_mode = true;
935 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
939 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
940 struct device *dev = i2c_dev->dev;
941 void __iomem *base = i2c_dev->base;
946 reinit_completion(&i2c_dev->complete);
1067 i2c_dev->use_dma = false;
1068 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1069 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1073 i2c_dev);
1075 i2c_dev->use_dma = true;
1077 dev_warn(i2c_dev->dev, "can't use DMA\n");
1080 if (!i2c_dev->use_dma) {
1095 i2c_dev->master_mode = true;
1104 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1106 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1107 void __iomem *base = i2c_dev->base;
1159 i2c_dev->use_dma = false;
1160 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1163 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1167 i2c_dev);
1170 i2c_dev->use_dma = true;
1172 dev_warn(i2c_dev->dev, "can't use DMA\n");
1175 if (!i2c_dev->use_dma)
1188 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1190 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1193 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1210 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1215 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1249 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1251 struct i2c_client *slave = i2c_dev->slave_running;
1252 void __iomem *base = i2c_dev->base;
1256 if (i2c_dev->slave_dir) {
1297 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1299 void __iomem *base = i2c_dev->base;
1303 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1308 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1309 i2c_dev->slave_running = i2c_dev->slave[i];
1310 i2c_dev->slave_dir = dir;
1313 stm32f7_i2c_slave_start(i2c_dev);
1323 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1329 if (i2c_dev->slave[i] == slave) {
1335 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1340 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1343 struct device *dev = i2c_dev->dev;
1351 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1352 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1362 if (!i2c_dev->slave[i]) {
1374 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1379 if (i2c_dev->slave[i])
1386 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1392 if (i2c_dev->slave[i])
1399 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1401 void __iomem *base = i2c_dev->base;
1406 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1410 i2c_slave_event(i2c_dev->slave_running,
1424 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1425 ret = i2c_slave_event(i2c_dev->slave_running,
1429 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1431 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1440 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1447 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1449 if (i2c_dev->slave_dir) {
1462 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1464 i2c_dev->slave_running = NULL;
1469 stm32f7_i2c_slave_addr(i2c_dev);
1476 struct stm32f7_i2c_dev *i2c_dev = data;
1477 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1478 struct stm32_i2c_dma *dma = i2c_dev->dma;
1479 void __iomem *base = i2c_dev->base;
1484 if (!i2c_dev->master_mode) {
1485 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1489 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1493 stm32f7_i2c_write_tx_data(i2c_dev);
1497 stm32f7_i2c_read_rx_data(i2c_dev);
1501 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1504 if (i2c_dev->use_dma) {
1505 stm32f7_i2c_disable_dma_req(i2c_dev);
1514 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1518 stm32f7_i2c_disable_irq(i2c_dev, mask);
1523 if (i2c_dev->use_dma && !f7_msg->result) {
1526 i2c_dev->master_mode = false;
1527 complete(&i2c_dev->complete);
1536 } else if (i2c_dev->use_dma && !f7_msg->result) {
1539 stm32f7_i2c_smbus_rep_start(i2c_dev);
1541 i2c_dev->msg_id++;
1542 i2c_dev->msg++;
1543 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1549 stm32f7_i2c_smbus_reload(i2c_dev);
1551 stm32f7_i2c_reload(i2c_dev);
1559 struct stm32f7_i2c_dev *i2c_dev = data;
1560 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1561 struct stm32_i2c_dma *dma = i2c_dev->dma;
1569 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1571 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1572 stm32f7_i2c_disable_dma_req(i2c_dev);
1577 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1581 stm32f7_i2c_smbus_rep_start(i2c_dev);
1583 i2c_dev->msg_id++;
1584 i2c_dev->msg++;
1585 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1588 i2c_dev->master_mode = false;
1589 complete(&i2c_dev->complete);
1597 struct stm32f7_i2c_dev *i2c_dev = data;
1598 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1599 void __iomem *base = i2c_dev->base;
1600 struct device *dev = i2c_dev->dev;
1601 struct stm32_i2c_dma *dma = i2c_dev->dma;
1604 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1610 stm32f7_i2c_release_bus(&i2c_dev->adap);
1627 if (!i2c_dev->slave_running) {
1630 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1634 stm32f7_i2c_disable_irq(i2c_dev, mask);
1638 if (i2c_dev->use_dma) {
1639 stm32f7_i2c_disable_dma_req(i2c_dev);
1643 i2c_dev->master_mode = false;
1644 complete(&i2c_dev->complete);
1652 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1653 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1654 struct stm32_i2c_dma *dma = i2c_dev->dma;
1658 i2c_dev->msg = msgs;
1659 i2c_dev->msg_num = num;
1660 i2c_dev->msg_id = 0;
1663 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1667 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1671 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1673 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1674 i2c_dev->adap.timeout);
1683 i2c_dev->base + STM32F7_I2C_ISR);
1688 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1689 i2c_dev->msg->addr);
1690 if (i2c_dev->use_dma)
1692 stm32f7_i2c_wait_free_bus(i2c_dev);
1697 pm_runtime_mark_last_busy(i2c_dev->dev);
1698 pm_runtime_put_autosuspend(i2c_dev->dev);
1708 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1709 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1710 struct stm32_i2c_dma *dma = i2c_dev->dma;
1711 struct device *dev = i2c_dev->dev;
1724 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1728 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1732 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1733 i2c_dev->adap.timeout);
1742 i2c_dev->base + STM32F7_I2C_ISR);
1748 if (i2c_dev->use_dma)
1750 stm32f7_i2c_wait_free_bus(i2c_dev);
1757 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1790 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1793 void __iomem *base = i2c_dev->base;
1796 if (!i2c_dev->wakeup_src)
1800 device_set_wakeup_enable(i2c_dev->dev, true);
1803 device_set_wakeup_enable(i2c_dev->dev, false);
1810 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1811 void __iomem *base = i2c_dev->base;
1812 struct device *dev = i2c_dev->dev;
1821 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1826 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1834 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1835 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1840 i2c_dev->slave[id] = slave;
1845 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1854 i2c_dev->slave[id] = slave;
1855 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1860 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1869 i2c_dev->slave[id] = slave;
1870 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1889 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1890 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1900 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1901 void __iomem *base = i2c_dev->base;
1905 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1909 WARN_ON(!i2c_dev->slave[id]);
1911 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1923 i2c_dev->slave[id] = NULL;
1925 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1926 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1927 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1930 pm_runtime_mark_last_busy(i2c_dev->dev);
1931 pm_runtime_put_autosuspend(i2c_dev->dev);
1936 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1941 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1942 IS_ERR_OR_NULL(i2c_dev->regmap))
1946 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1947 ret = regmap_update_bits(i2c_dev->regmap,
1948 i2c_dev->fmp_sreg,
1949 i2c_dev->fmp_mask,
1950 enable ? i2c_dev->fmp_mask : 0);
1952 ret = regmap_write(i2c_dev->regmap,
1953 enable ? i2c_dev->fmp_sreg :
1954 i2c_dev->fmp_creg,
1955 i2c_dev->fmp_mask);
1961 struct stm32f7_i2c_dev *i2c_dev)
1966 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1967 if (IS_ERR(i2c_dev->regmap))
1972 &i2c_dev->fmp_sreg);
1976 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1977 i2c_dev->setup.fmp_clr_offset;
1980 &i2c_dev->fmp_mask);
1983 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1985 struct i2c_adapter *adap = &i2c_dev->adap;
1986 void __iomem *base = i2c_dev->base;
1993 i2c_dev->host_notify_client = client;
2001 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2003 void __iomem *base = i2c_dev->base;
2005 if (i2c_dev->host_notify_client) {
2009 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2015 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2024 if (i2c_dev->smbus_mode)
2040 struct stm32f7_i2c_dev *i2c_dev;
2048 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2049 if (!i2c_dev)
2052 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2053 if (IS_ERR(i2c_dev->base))
2054 return PTR_ERR(i2c_dev->base);
2073 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2076 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2077 if (IS_ERR(i2c_dev->clk))
2078 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2081 ret = clk_prepare_enable(i2c_dev->clk);
2097 i2c_dev->dev = &pdev->dev;
2103 pdev->name, i2c_dev);
2111 pdev->name, i2c_dev);
2124 i2c_dev->setup = *setup;
2126 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2131 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2132 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2135 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2140 adap = &i2c_dev->adap;
2141 i2c_set_adapdata(adap, i2c_dev);
2151 init_completion(&i2c_dev->complete);
2154 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2157 if (IS_ERR(i2c_dev->dma)) {
2158 ret = PTR_ERR(i2c_dev->dma);
2162 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2163 i2c_dev->dma = NULL;
2166 if (i2c_dev->wakeup_src) {
2167 device_set_wakeup_capable(i2c_dev->dev, true);
2169 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2171 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2176 platform_set_drvdata(pdev, i2c_dev);
2178 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2180 pm_runtime_use_autosuspend(i2c_dev->dev);
2181 pm_runtime_set_active(i2c_dev->dev);
2182 pm_runtime_enable(i2c_dev->dev);
2186 stm32f7_i2c_hw_config(i2c_dev);
2188 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2194 if (i2c_dev->smbus_mode) {
2195 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2197 dev_err(i2c_dev->dev,
2204 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2206 pm_runtime_mark_last_busy(i2c_dev->dev);
2207 pm_runtime_put_autosuspend(i2c_dev->dev);
2215 pm_runtime_put_noidle(i2c_dev->dev);
2216 pm_runtime_disable(i2c_dev->dev);
2217 pm_runtime_set_suspended(i2c_dev->dev);
2218 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2220 if (i2c_dev->wakeup_src)
2221 dev_pm_clear_wake_irq(i2c_dev->dev);
2224 if (i2c_dev->wakeup_src)
2225 device_set_wakeup_capable(i2c_dev->dev, false);
2227 if (i2c_dev->dma) {
2228 stm32_i2c_dma_free(i2c_dev->dma);
2229 i2c_dev->dma = NULL;
2233 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2236 clk_disable_unprepare(i2c_dev->clk);
2243 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2245 stm32f7_i2c_disable_smbus_host(i2c_dev);
2247 i2c_del_adapter(&i2c_dev->adap);
2248 pm_runtime_get_sync(i2c_dev->dev);
2250 if (i2c_dev->wakeup_src) {
2251 dev_pm_clear_wake_irq(i2c_dev->dev);
2256 device_init_wakeup(i2c_dev->dev, false);
2259 pm_runtime_put_noidle(i2c_dev->dev);
2260 pm_runtime_disable(i2c_dev->dev);
2261 pm_runtime_set_suspended(i2c_dev->dev);
2262 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2264 if (i2c_dev->dma) {
2265 stm32_i2c_dma_free(i2c_dev->dma);
2266 i2c_dev->dma = NULL;
2269 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2271 clk_disable_unprepare(i2c_dev->clk);
2278 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2280 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2281 clk_disable_unprepare(i2c_dev->clk);
2288 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2291 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2292 ret = clk_prepare_enable(i2c_dev->clk);
2303 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2306 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2308 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2312 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2313 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2314 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2315 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2316 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2317 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2319 pm_runtime_put_sync(i2c_dev->dev);
2324 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2328 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2330 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2334 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2336 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2339 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2341 i2c_dev->base + STM32F7_I2C_CR1);
2343 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2345 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2346 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2347 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2348 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2350 pm_runtime_put_sync(i2c_dev->dev);
2357 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2360 i2c_mark_adapter_suspended(&i2c_dev->adap);
2363 ret = stm32f7_i2c_regs_backup(i2c_dev);
2365 i2c_mark_adapter_resumed(&i2c_dev->adap);
2378 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2387 ret = stm32f7_i2c_regs_restore(i2c_dev);
2392 i2c_mark_adapter_resumed(&i2c_dev->adap);