Lines Matching defs:frequency
61 * SMBus Master core clock frequency. Timing configurations are
62 * strongly dependent on the core clock frequency of the SMBus
69 /* Constant used to determine the PLL frequency. */
184 * Defines SMBus operating frequency and core clock frequency.
187 * frequency based on PLL parameters.
202 /* Core PLL frequency. */
421 /* Callback to calculate the core PLL frequency. */
432 u64 frequency; /* Core frequency in Hz. */
473 /* Polling frequency in microseconds. */
1080 u64 frequency;
1090 frequency = priv->frequency;
1091 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;
1170 * bus frequency, it is impacted by the time it takes the driver to
1233 ret = device_property_read_u32(dev, "clock-frequency", &config_khz);
1461 * Compute PLL output frequency as follow:
1492 * Compute PLL output frequency as follow:
1513 u64 *freq = &priv->frequency;
1522 * First, check whether the TYU core Clock frequency is set.
1523 * The TYU core frequency is the same for all I2C busses; when
1524 * the first device gets probed the frequency is determined and
1526 * check whether the frequency is already set. Here, we assume
1527 * that the frequency is expected to be greater than 0.
2371 /* Read Core PLL frequency. */
2374 dev_err(dev, "cannot get core clock frequency\n");
2376 priv->frequency = MLXBF_I2C_COREPLL_FREQ;