Lines Matching refs:dev
26 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
29 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
30 regmap_write(dev->map, DW_IC_RX_TL, 0);
33 regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
41 struct i2c_timings *t = &dev->timings;
45 ret = i2c_dw_acquire_lock(dev);
49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
50 i2c_dw_release_lock(dev);
59 if (!dev->ss_hcnt || !dev->ss_lcnt) {
60 ic_clk = i2c_dw_clk_rate(dev);
61 dev->ss_hcnt =
67 dev->ss_lcnt =
73 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
74 dev->ss_hcnt, dev->ss_lcnt);
86 if (dev->fp_hcnt && dev->fp_lcnt) {
87 dev->fs_hcnt = dev->fp_hcnt;
88 dev->fs_lcnt = dev->fp_lcnt;
90 ic_clk = i2c_dw_clk_rate(dev);
91 dev->fs_hcnt =
97 dev->fs_lcnt =
109 if (!dev->fs_hcnt || !dev->fs_lcnt) {
110 ic_clk = i2c_dw_clk_rate(dev);
111 dev->fs_hcnt =
117 dev->fs_lcnt =
123 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
124 fp_str, dev->fs_hcnt, dev->fs_lcnt);
127 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
131 dev_err(dev->dev, "High Speed not supported!\n");
133 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
134 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
135 dev->hs_hcnt = 0;
136 dev->hs_lcnt = 0;
137 } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
138 ic_clk = i2c_dw_clk_rate(dev);
139 dev->hs_hcnt =
145 dev->hs_lcnt =
151 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
152 dev->hs_hcnt, dev->hs_lcnt);
155 ret = i2c_dw_set_sda_hold(dev);
159 switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
169 dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
177 * @dev: device private data
183 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
187 ret = i2c_dw_acquire_lock(dev);
192 __i2c_dw_disable(dev);
195 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
196 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
199 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
200 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
203 if (dev->hs_hcnt && dev->hs_lcnt) {
204 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
205 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
209 if (dev->sda_hold_time)
210 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
212 i2c_dw_configure_fifo_master(dev);
213 i2c_dw_release_lock(dev);
218 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
220 struct i2c_msg *msgs = dev->msgs;
225 __i2c_dw_disable(dev);
228 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
239 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
246 regmap_write(dev->map, DW_IC_TAR,
247 msgs[dev->msg_write_idx].addr | ic_tar);
250 i2c_dw_disable_int(dev);
253 __i2c_dw_enable(dev);
256 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
259 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
260 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
270 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
272 struct i2c_msg *msgs = dev->msgs;
275 u32 addr = msgs[dev->msg_write_idx].addr;
276 u32 buf_len = dev->tx_buf_len;
277 u8 *buf = dev->tx_buf;
283 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
284 u32 flags = msgs[dev->msg_write_idx].flags;
291 if (msgs[dev->msg_write_idx].addr != addr) {
292 dev_err(dev->dev,
294 dev->msg_err = -EINVAL;
298 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
300 buf = msgs[dev->msg_write_idx].buf;
301 buf_len = msgs[dev->msg_write_idx].len;
307 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
308 (dev->msg_write_idx > 0))
312 regmap_read(dev->map, DW_IC_TXFLR, &flr);
313 tx_limit = dev->tx_fifo_depth - flr;
315 regmap_read(dev->map, DW_IC_RXFLR, &flr);
316 rx_limit = dev->rx_fifo_depth - flr;
334 if (dev->msg_write_idx == dev->msgs_num - 1 &&
343 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
346 if (dev->rx_outstanding >= dev->rx_fifo_depth)
349 regmap_write(dev->map, DW_IC_DATA_CMD,
352 dev->rx_outstanding++;
354 regmap_write(dev->map, DW_IC_DATA_CMD,
360 dev->tx_buf = buf;
361 dev->tx_buf_len = buf_len;
371 dev->status |= STATUS_WRITE_IN_PROGRESS;
376 dev->status |= STATUS_WRITE_IN_PROGRESS;
379 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
386 if (dev->msg_write_idx == dev->msgs_num)
389 if (dev->msg_err)
392 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
396 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
398 struct i2c_msg *msgs = dev->msgs;
399 u32 flags = msgs[dev->msg_read_idx].flags;
406 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
407 msgs[dev->msg_read_idx].len = len;
408 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
414 regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY,
421 i2c_dw_read(struct dw_i2c_dev *dev)
423 struct i2c_msg *msgs = dev->msgs;
426 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
430 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
433 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
434 len = msgs[dev->msg_read_idx].len;
435 buf = msgs[dev->msg_read_idx].buf;
437 len = dev->rx_buf_len;
438 buf = dev->rx_buf;
441 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
444 u32 flags = msgs[dev->msg_read_idx].flags;
446 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
461 len = i2c_dw_recv_len(dev, tmp);
464 dev->rx_outstanding--;
468 dev->status |= STATUS_READ_IN_PROGRESS;
469 dev->rx_buf_len = len;
470 dev->rx_buf = buf;
473 dev->status &= ~STATUS_READ_IN_PROGRESS;
483 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
486 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
488 pm_runtime_get_sync(dev->dev);
490 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
495 reinit_completion(&dev->cmd_complete);
496 dev->msgs = msgs;
497 dev->msgs_num = num;
498 dev->cmd_err = 0;
499 dev->msg_write_idx = 0;
500 dev->msg_read_idx = 0;
501 dev->msg_err = 0;
502 dev->status = STATUS_IDLE;
503 dev->abort_source = 0;
504 dev->rx_outstanding = 0;
506 ret = i2c_dw_acquire_lock(dev);
510 ret = i2c_dw_wait_bus_not_busy(dev);
515 i2c_dw_xfer_init(dev);
518 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
519 dev_err(dev->dev, "controller timed out\n");
521 i2c_recover_bus(&dev->adapter);
522 i2c_dw_init_master(dev);
535 __i2c_dw_disable_nowait(dev);
537 if (dev->msg_err) {
538 ret = dev->msg_err;
543 if (likely(!dev->cmd_err && !dev->status)) {
549 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
550 ret = i2c_dw_handle_tx_abort(dev);
554 if (dev->status)
555 dev_err(dev->dev,
561 i2c_dw_release_lock(dev);
564 pm_runtime_mark_last_busy(dev->dev);
565 pm_runtime_put_autosuspend(dev->dev);
579 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
595 regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
605 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
607 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
609 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
611 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
617 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
618 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
621 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
623 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
625 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
627 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
629 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
638 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
642 stat = i2c_dw_read_clear_intrbits(dev);
644 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
645 dev->status = STATUS_IDLE;
651 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
656 i2c_dw_read(dev);
659 i2c_dw_xfer_msg(dev);
668 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
669 complete(&dev->cmd_complete);
670 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
672 regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
673 i2c_dw_disable_int(dev);
674 regmap_write(dev->map, DW_IC_INTR_MASK, stat);
682 struct dw_i2c_dev *dev = dev_id;
685 regmap_read(dev->map, DW_IC_ENABLE, &enabled);
686 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
687 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
691 i2c_dw_irq_handler_master(dev);
696 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
698 struct i2c_timings *t = &dev->timings;
700 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
702 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
705 dev->mode = DW_IC_MASTER;
709 dev->master_cfg |= DW_IC_CON_SPEED_STD;
712 dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
715 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
722 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
724 i2c_dw_disable(dev);
725 reset_control_assert(dev->rst);
726 i2c_dw_prepare_clk(dev, false);
731 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
733 i2c_dw_prepare_clk(dev, true);
734 reset_control_deassert(dev->rst);
735 i2c_dw_init_master(dev);
738 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
740 struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
741 struct i2c_adapter *adap = &dev->adapter;
744 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
750 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
760 dev_info(dev->dev, "running with gpio recovery mode! scl%s",
766 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
768 struct i2c_adapter *adap = &dev->adapter;
772 init_completion(&dev->cmd_complete);
774 dev->init = i2c_dw_init_master;
775 dev->disable = i2c_dw_disable;
776 dev->disable_int = i2c_dw_disable_int;
778 ret = i2c_dw_init_regmap(dev);
782 ret = i2c_dw_set_timings_master(dev);
786 ret = i2c_dw_set_fifo_size(dev);
790 ret = dev->init(dev);
799 adap->dev.parent = dev->dev;
800 i2c_set_adapdata(adap, dev);
802 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
808 i2c_dw_disable_int(dev);
809 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
810 dev_name(dev->dev), dev);
812 dev_err(dev->dev, "failure requesting irq %i: %d\n",
813 dev->irq, ret);
817 ret = i2c_dw_init_recovery_info(dev);
827 pm_runtime_get_noresume(dev->dev);
830 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
831 pm_runtime_put_noidle(dev->dev);