Lines Matching refs:val
244 u32 val;
251 val = readl(iproc_i2c->base + offset);
254 val = readl(iproc_i2c->base + offset);
257 return val;
261 u32 offset, u32 val)
269 writel(val, iproc_i2c->base + offset);
272 writel(val, iproc_i2c->base + offset);
279 u32 val;
284 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
285 val |= BIT(CFG_RESET_SHIFT);
286 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
292 val &= ~(BIT(CFG_RESET_SHIFT));
293 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
297 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
298 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
301 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
302 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
303 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
304 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
307 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
308 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
309 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
310 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
311 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
317 val = BIT(IE_S_RX_EVENT_SHIFT);
319 val |= BIT(IE_S_RD_EVENT_SHIFT);
321 val |= BIT(IE_S_START_BUSY_SHIFT);
322 iproc_i2c->slave_int_mask = val;
323 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
329 u32 val;
331 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
333 if (val & BIT(S_CMD_START_BUSY_SHIFT))
336 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
337 if (val == S_CMD_STATUS_TIMEOUT) {
351 u32 val;
354 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
355 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
356 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
426 u32 val;
442 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
443 val &= ~iproc_i2c->slave_int_mask;
444 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
476 val = BIT(S_CMD_START_BUSY_SHIFT);
477 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
495 val = BIT(S_TX_WR_STATUS_SHIFT);
496 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
498 val = BIT(S_CMD_START_BUSY_SHIFT);
499 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
502 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
503 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
504 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
523 uint32_t val;
527 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
530 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
534 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
544 u32 val;
552 val = msg->buf[idx];
556 val |= BIT(M_TX_WR_STATUS_SHIFT);
573 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
583 u32 bytes_left, val;
590 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
591 val &= ~BIT(IS_M_RX_THLD_SHIFT);
592 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
596 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
597 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
598 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
599 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
661 u32 val;
664 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
665 val |= BIT(CFG_RESET_SHIFT);
666 val &= ~(BIT(CFG_EN_SHIFT));
667 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
673 val &= ~(BIT(CFG_RESET_SHIFT));
674 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
677 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
678 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
680 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
681 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
683 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
694 u32 val;
696 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
698 val |= BIT(CFG_EN_SHIFT);
700 val &= ~BIT(CFG_EN_SHIFT);
701 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
707 u32 val;
709 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
710 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
712 switch (val) {
741 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
757 u32 val, status;
795 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
796 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
803 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
804 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
822 u32 val, tmp, val_intr_en;
847 val = msg->buf[i];
851 val |= BIT(M_TX_WR_STATUS_SHIFT);
853 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
869 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
870 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
899 val = BIT(M_CMD_START_BUSY_SHIFT);
903 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
925 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
928 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
934 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
964 u32 val;
966 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
969 val |= I2C_FUNC_SLAVE;
971 return val;
990 u32 val;
1012 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1013 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1014 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1015 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1154 u32 val;
1165 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1166 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1167 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1168 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);