Lines Matching refs:cmt
92 struct sh_cmt_device *cmt;
245 return ch->cmt->info->read_control(ch->iostart, 0);
247 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
256 ch->cmt->info->write_control(ch->iostart, 0, value);
257 udelay(ch->cmt->reg_delay);
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
260 udelay(ch->cmt->reg_delay);
267 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
275 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
276 udelay(ch->cmt->reg_delay);
282 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
288 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
291 if (ch->cmt->info->model > SH_CMT_16BIT) {
299 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
306 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
309 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
310 udelay(ch->cmt->reg_delay);
319 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
327 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
341 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
350 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
357 pm_runtime_get_sync(&ch->cmt->pdev->dev);
358 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
361 ret = clk_enable(ch->cmt->clk);
363 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
372 if (ch->cmt->info->width == 16) {
386 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
397 clk_disable(ch->cmt->clk);
412 clk_disable(ch->cmt->clk);
414 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
415 pm_runtime_put(&ch->cmt->pdev->dev);
505 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
514 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
536 ch->cmt->info->clear_bits);
593 if (ch->cmt->num_channels == 1 &&
632 if (ch->cmt->num_channels == 1) {
685 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
695 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
711 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
714 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
717 clocksource_register_hz(cs, ch->cmt->rate);
731 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
753 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
787 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
788 clk_unprepare(ch->cmt->clk);
795 clk_prepare(ch->cmt->clk);
796 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
806 irq = platform_get_irq(ch->cmt->pdev, ch->index);
812 dev_name(&ch->cmt->pdev->dev), ch);
814 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
833 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
839 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
852 ch->cmt->has_clockevent = true;
859 ch->cmt->has_clocksource = true;
868 bool clocksource, struct sh_cmt_device *cmt)
877 ch->cmt = cmt;
887 switch (cmt->info->model) {
889 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
893 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
897 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
902 value = ioread32(cmt->mapbase + CMCLKE);
904 iowrite32(value, cmt->mapbase + CMCLKE);
908 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
911 ch->max_match_value = (1 << cmt->info->width) - 1;
916 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
919 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
928 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
932 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
934 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
938 cmt->mapbase = ioremap(mem->start, resource_size(mem));
939 if (cmt->mapbase == NULL) {
940 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
948 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
949 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
957 .compatible = "renesas,cmt-48",
962 .compatible = "renesas,cmt-48-gen2",
993 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
999 cmt->pdev = pdev;
1000 raw_spin_lock_init(&cmt->lock);
1003 cmt->info = of_device_get_match_data(&pdev->dev);
1004 cmt->hw_channels = cmt->info->channels_mask;
1009 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1010 cmt->hw_channels = cfg->channels_mask;
1012 dev_err(&cmt->pdev->dev, "missing platform data\n");
1017 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1018 if (IS_ERR(cmt->clk)) {
1019 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1020 return PTR_ERR(cmt->clk);
1023 ret = clk_prepare(cmt->clk);
1028 ret = clk_enable(cmt->clk);
1032 rate = clk_get_rate(cmt->clk);
1039 if (cmt->info->model >= SH_CMT_48BIT)
1040 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate);
1041 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8);
1044 ret = sh_cmt_map_memory(cmt);
1049 cmt->num_channels = hweight8(cmt->hw_channels);
1050 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1052 if (cmt->channels == NULL) {
1061 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1063 bool clocksource = i == 1 || cmt->num_channels == 1;
1066 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1067 clockevent, clocksource, cmt);
1074 clk_disable(cmt->clk);
1076 platform_set_drvdata(pdev, cmt);
1081 kfree(cmt->channels);
1082 iounmap(cmt->mapbase);
1084 clk_disable(cmt->clk);
1086 clk_unprepare(cmt->clk);
1088 clk_put(cmt->clk);
1094 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1102 if (cmt) {
1107 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1108 if (cmt == NULL)
1111 ret = sh_cmt_setup(cmt, pdev);
1113 kfree(cmt);
1121 if (cmt->has_clockevent || cmt->has_clocksource)