Lines Matching refs:ch
242 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
244 if (ch->iostart)
245 return ch->cmt->info->read_control(ch->iostart, 0);
247 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
250 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
252 u32 old_value = sh_cmt_read_cmstr(ch);
255 if (ch->iostart) {
256 ch->cmt->info->write_control(ch->iostart, 0, value);
257 udelay(ch->cmt->reg_delay);
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
260 udelay(ch->cmt->reg_delay);
265 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
267 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
270 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
272 u32 old_value = sh_cmt_read_cmcsr(ch);
275 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
276 udelay(ch->cmt->reg_delay);
280 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
282 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
285 static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
288 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
291 if (ch->cmt->info->model > SH_CMT_16BIT) {
294 1, cmcnt_delay, false, ch);
299 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
304 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
306 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
309 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
310 udelay(ch->cmt->reg_delay);
314 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
319 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
324 v1 = sh_cmt_read_cmcnt(ch);
325 v2 = sh_cmt_read_cmcnt(ch);
326 v3 = sh_cmt_read_cmcnt(ch);
327 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
335 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
341 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
342 value = sh_cmt_read_cmstr(ch);
345 value |= 1 << ch->timer_bit;
347 value &= ~(1 << ch->timer_bit);
349 sh_cmt_write_cmstr(ch, value);
350 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
353 static int sh_cmt_enable(struct sh_cmt_channel *ch)
357 pm_runtime_get_sync(&ch->cmt->pdev->dev);
358 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
361 ret = clk_enable(ch->cmt->clk);
363 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
364 ch->index);
369 sh_cmt_start_stop_ch(ch, 0);
372 if (ch->cmt->info->width == 16) {
373 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
376 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
382 sh_cmt_write_cmcor(ch, 0xffffffff);
383 ret = sh_cmt_write_cmcnt(ch, 0);
385 if (ret || sh_cmt_read_cmcnt(ch)) {
386 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
387 ch->index);
393 sh_cmt_start_stop_ch(ch, 1);
397 clk_disable(ch->cmt->clk);
403 static void sh_cmt_disable(struct sh_cmt_channel *ch)
406 sh_cmt_start_stop_ch(ch, 0);
409 sh_cmt_write_cmcsr(ch, 0);
412 clk_disable(ch->cmt->clk);
414 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
415 pm_runtime_put(&ch->cmt->pdev->dev);
425 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
428 u32 value = ch->next_match_value;
434 now = sh_cmt_get_counter(ch, &has_wrapped);
435 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
442 ch->flags |= FLAG_SKIPEVENT;
454 if (new_match > ch->max_match_value)
455 new_match = ch->max_match_value;
457 sh_cmt_write_cmcor(ch, new_match);
459 now = sh_cmt_get_counter(ch, &has_wrapped);
460 if (has_wrapped && (new_match > ch->match_value)) {
467 ch->flags |= FLAG_SKIPEVENT;
478 ch->match_value = new_match;
489 ch->match_value = new_match;
505 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
506 ch->index);
511 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
513 if (delta > ch->max_match_value)
514 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
515 ch->index);
517 ch->next_match_value = delta;
518 sh_cmt_clock_event_program_verify(ch, 0);
521 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
525 raw_spin_lock_irqsave(&ch->lock, flags);
526 __sh_cmt_set_next(ch, delta);
527 raw_spin_unlock_irqrestore(&ch->lock, flags);
532 struct sh_cmt_channel *ch = dev_id;
535 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
536 ch->cmt->info->clear_bits);
542 if (ch->flags & FLAG_CLOCKSOURCE)
543 ch->total_cycles += ch->match_value + 1;
545 if (!(ch->flags & FLAG_REPROGRAM))
546 ch->next_match_value = ch->max_match_value;
548 ch->flags |= FLAG_IRQCONTEXT;
550 if (ch->flags & FLAG_CLOCKEVENT) {
551 if (!(ch->flags & FLAG_SKIPEVENT)) {
552 if (clockevent_state_oneshot(&ch->ced)) {
553 ch->next_match_value = ch->max_match_value;
554 ch->flags |= FLAG_REPROGRAM;
557 ch->ced.event_handler(&ch->ced);
561 ch->flags &= ~FLAG_SKIPEVENT;
563 if (ch->flags & FLAG_REPROGRAM) {
564 ch->flags &= ~FLAG_REPROGRAM;
565 sh_cmt_clock_event_program_verify(ch, 1);
567 if (ch->flags & FLAG_CLOCKEVENT)
568 if ((clockevent_state_shutdown(&ch->ced))
569 || (ch->match_value == ch->next_match_value))
570 ch->flags &= ~FLAG_REPROGRAM;
573 ch->flags &= ~FLAG_IRQCONTEXT;
578 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
583 raw_spin_lock_irqsave(&ch->lock, flags);
585 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
586 ret = sh_cmt_enable(ch);
590 ch->flags |= flag;
593 if (ch->cmt->num_channels == 1 &&
594 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
595 __sh_cmt_set_next(ch, ch->max_match_value);
597 raw_spin_unlock_irqrestore(&ch->lock, flags);
602 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
607 raw_spin_lock_irqsave(&ch->lock, flags);
609 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
610 ch->flags &= ~flag;
612 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
613 sh_cmt_disable(ch);
616 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
617 __sh_cmt_set_next(ch, ch->max_match_value);
619 raw_spin_unlock_irqrestore(&ch->lock, flags);
629 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
632 if (ch->cmt->num_channels == 1) {
637 raw_spin_lock_irqsave(&ch->lock, flags);
638 value = ch->total_cycles;
639 raw = sh_cmt_get_counter(ch, &has_wrapped);
642 raw += ch->match_value + 1;
643 raw_spin_unlock_irqrestore(&ch->lock, flags);
648 return sh_cmt_get_counter(ch, &has_wrapped);
654 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
656 WARN_ON(ch->cs_enabled);
658 ch->total_cycles = 0;
660 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
662 ch->cs_enabled = true;
669 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
671 WARN_ON(!ch->cs_enabled);
673 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
674 ch->cs_enabled = false;
679 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
681 if (!ch->cs_enabled)
684 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
685 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
690 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
692 if (!ch->cs_enabled)
695 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
696 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
699 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
702 struct clocksource *cs = &ch->cs;
711 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
714 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
715 ch->index);
717 clocksource_register_hz(cs, ch->cmt->rate);
726 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
728 sh_cmt_start(ch, FLAG_CLOCKEVENT);
731 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
733 sh_cmt_set_next(ch, ch->max_match_value);
738 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
740 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
747 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
751 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
753 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
754 ch->index, periodic ? "periodic" : "oneshot");
755 sh_cmt_clock_event_start(ch, periodic);
772 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
775 if (likely(ch->flags & FLAG_IRQCONTEXT))
776 ch->next_match_value = delta - 1;
778 sh_cmt_set_next(ch, delta - 1);
785 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
787 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
788 clk_unprepare(ch->cmt->clk);
793 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
795 clk_prepare(ch->cmt->clk);
796 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
799 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
802 struct clock_event_device *ced = &ch->ced;
806 irq = platform_get_irq(ch->cmt->pdev, ch->index);
812 dev_name(&ch->cmt->pdev->dev), ch);
814 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
815 ch->index, irq);
833 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
834 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
835 ced->max_delta_ticks = ch->max_match_value;
839 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
840 ch->index);
846 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
852 ch->cmt->has_clockevent = true;
853 ret = sh_cmt_register_clockevent(ch, name);
859 ch->cmt->has_clocksource = true;
860 sh_cmt_register_clocksource(ch, name);
866 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
877 ch->cmt = cmt;
878 ch->index = index;
879 ch->hwidx = hwidx;
880 ch->timer_bit = hwidx;
889 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
893 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
897 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
898 ch->ioctrl = ch->iostart + 0x10;
899 ch->timer_bit = 0;
908 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
909 ch->max_match_value = ~0;
911 ch->max_match_value = (1 << cmt->info->width) - 1;
913 ch->match_value = ch->max_match_value;
914 raw_spin_lock_init(&ch->lock);
916 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
919 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
920 ch->index);
923 ch->cs_enabled = false;