Lines Matching refs:rate
93 * @rate: Desired clock frequency
96 * Return: Frequency closest to @rate the hardware can generate
98 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
104 /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
105 if (rate > PS_PLL_VCO_MAX) {
106 div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
107 rate = rate / div;
109 if (rate < PS_PLL_VCO_MIN) {
110 mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
111 rate = rate * mult;
114 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
117 rate = *prate * fbdiv;
120 return rate;
137 unsigned long rate, frac;
146 rate = parent_rate * fbdiv;
151 rate = rate + frac;
154 return rate;
158 * zynqmp_pll_set_rate() - Set rate of PLL
160 * @rate: Frequency of clock to be set
163 * Set PLL divider to set desired rate.
165 * Returns: rate which is set on success else error code
167 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
177 rate_div = (rate * FRAC_DIV) / parent_rate;
184 rate = parent_rate * m;
196 return rate + frac;
199 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);