Lines Matching refs:clk_id
16 * @clk_id: PLL clock ID
21 u32 clk_id;
51 u32 clk_id = clk->clk_id;
56 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
72 u32 clk_id = clk->clk_id;
82 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
134 u32 clk_id = clk->clk_id;
141 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
148 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload);
171 u32 clk_id = clk->clk_id;
187 ret = zynqmp_pm_clock_setdivider(clk_id, m);
194 zynqmp_pm_set_pll_frac_data(clk_id, f);
201 ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
219 u32 clk_id = clk->clk_id;
223 ret = zynqmp_pm_clock_getstate(clk_id, &state);
243 u32 clk_id = clk->clk_id;
255 ret = zynqmp_pm_clock_enable(clk_id);
271 u32 clk_id = clk->clk_id;
277 ret = zynqmp_pm_clock_disable(clk_id);
295 * @clk_id: Clock ID
302 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
323 pll->clk_id = clk_id;