Lines Matching refs:ctxt
38 static void msr_save_context(struct saved_context *ctxt)
40 struct saved_msr *msr = ctxt->saved_msrs.array;
41 struct saved_msr *end = msr + ctxt->saved_msrs.num;
50 static void msr_restore_context(struct saved_context *ctxt)
52 struct saved_msr *msr = ctxt->saved_msrs.array;
53 struct saved_msr *end = msr + ctxt->saved_msrs.num;
65 * @ctxt - structure to store the registers contents in
77 static void __save_processor_state(struct saved_context *ctxt)
87 store_idt(&ctxt->idt);
95 ctxt->gdt_desc.size = GDT_SIZE - 1;
96 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
98 store_tr(ctxt->tr);
105 savesegment(gs, ctxt->gs);
108 savesegment(gs, ctxt->gs);
109 savesegment(fs, ctxt->fs);
110 savesegment(ds, ctxt->ds);
111 savesegment(es, ctxt->es);
113 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
114 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
115 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
118 rdmsrl(MSR_EFER, ctxt->efer);
124 ctxt->cr0 = read_cr0();
125 ctxt->cr2 = read_cr2();
126 ctxt->cr3 = __read_cr3();
127 ctxt->cr4 = __read_cr4();
128 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
129 &ctxt->misc_enable);
130 msr_save_context(ctxt);
191 * @ctxt - structure to load the registers contents from
196 static void notrace __restore_processor_state(struct saved_context *ctxt)
200 if (ctxt->misc_enable_saved)
201 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
207 if (ctxt->cr4)
208 __write_cr4(ctxt->cr4);
211 wrmsrl(MSR_EFER, ctxt->efer);
212 __write_cr4(ctxt->cr4);
214 write_cr3(ctxt->cr3);
215 write_cr2(ctxt->cr2);
216 write_cr0(ctxt->cr0);
219 load_idt(&ctxt->idt);
234 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
248 loadsegment(ds, ctxt->es);
249 loadsegment(es, ctxt->es);
250 loadsegment(fs, ctxt->fs);
251 load_gs_index(ctxt->gs);
258 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
259 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
261 loadsegment(gs, ctxt->gs);
280 msr_restore_context(ctxt);