Lines Matching refs:val
68 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
80 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
81 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
82 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
83 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
84 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
85 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
86 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
87 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
88 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
89 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
90 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
91 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
92 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
93 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
94 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
95 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
96 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
97 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
98 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
99 case PAR_EL1: *val = read_sysreg_par(); break;
100 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
101 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
102 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
109 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
120 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
121 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
122 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
123 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
124 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
125 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
126 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
127 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
128 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
129 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
130 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
131 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
132 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
133 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
134 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
135 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
136 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
137 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
138 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
139 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
140 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
141 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
142 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
151 u64 val = 0x8badf00d8badf00d;
154 __vcpu_read_sys_reg_from_cpu(reg, &val))
155 return val;
160 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
163 __vcpu_write_sys_reg_to_cpu(val, reg))
166 __vcpu_sys_reg(vcpu, reg) = val;
223 u64 val;
233 val = p->regval;
235 val = vcpu_read_sys_reg(vcpu, reg);
237 val = (p->regval << 32) | (u64)lower_32_bits(val);
239 val = ((u64)upper_32_bits(val) << 32) |
242 vcpu_write_sys_reg(vcpu, val, reg);
354 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
358 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
449 u64 val = p->regval;
452 val &= 0xffffffffUL;
453 val |= ((*dbg_reg >> 32) << 32);
456 *dbg_reg = val;
508 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
551 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
594 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
636 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
670 u64 pmcr, val;
681 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
684 val |= ARMV8_PMU_PMCR_LC;
685 __vcpu_sys_reg(vcpu, r->reg) = val;
722 u64 val;
732 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
733 val &= ~ARMV8_PMU_PMCR_MASK;
734 val |= p->regval & ARMV8_PMU_PMCR_MASK;
736 val |= ARMV8_PMU_PMCR_LC;
737 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
738 kvm_pmu_handle_pmcr(vcpu, val);
742 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
744 p->regval = val;
791 u64 pmcr, val;
794 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
795 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
903 u64 val, mask;
913 val = p->regval & mask;
916 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
917 kvm_pmu_enable_counter_mask(vcpu, val);
921 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
922 kvm_pmu_disable_counter_mask(vcpu, val);
945 u64 val = p->regval & mask;
949 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
952 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
1127 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1131 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1132 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
1133 val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT);
1134 val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
1136 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
1138 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1144 val = cpuid_feature_cap_perfmon_field(val,
1149 val = cpuid_feature_cap_perfmon_field(val,
1154 return val;
1203 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1204 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1223 u64 val;
1226 err = reg_from_user(&val, uaddr, id);
1235 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1241 val ^= read_id_reg(vcpu, rd, false);
1242 val &= ~(0xFUL << ID_AA64PFR0_CSV2_SHIFT);
1243 if (val)
1263 const u64 val = read_id_reg(vcpu, rd, raz);
1265 return reg_to_user(uaddr, &val, id);
1274 u64 val;
1276 err = reg_from_user(&val, uaddr, id);
1281 if (val != read_id_reg(vcpu, rd, raz))
1846 u64 val = *dbg_reg;
1848 val &= 0xffffffffUL;
1849 val |= p->regval << 32;
1850 *dbg_reg = val;
2509 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2519 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2522 /* ->val is filled in by kvm_sys_reg_table_init() */
2531 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2533 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2538 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2540 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2555 return reg_to_user(uaddr, &r->val, id);
2563 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2570 err = reg_from_user(&val, uaddr, id);
2575 if (r->val != val)
2581 static bool is_valid_cache(u32 val)
2585 if (val >= CSSELR_MAX)
2589 level = (val >> 1);
2596 return (val & 1);
2599 return !(val & 1);
2609 u32 val;
2621 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2623 if (!is_valid_cache(val))
2626 return put_user(get_ccsidr(val), uval);
2634 u32 val, newval;
2646 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2648 if (!is_valid_cache(val))
2655 if (newval != get_ccsidr(val))
2726 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2729 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2733 if (put_user(val | i, uindices))
2858 cache_levels = clidr.val;