Lines Matching refs:ldr
27 1: ldr tmp1, [pmc, #AT91_PMC_SR]
36 1: ldr tmp1, [pmc, #AT91_PMC_SR]
45 1: ldr tmp1, [pmc, #AT91_PMC_SR]
87 ldr tmp1, [r0, #PM_DATA_PMC]
89 ldr tmp1, [r0, #PM_DATA_RAMC0]
91 ldr tmp1, [r0, #PM_DATA_RAMC1]
93 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
95 ldr tmp1, [r0, #PM_DATA_MODE]
97 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
99 ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
102 ldr tmp1, [r0, #PM_DATA_SHDWC]
106 ldr tmp1, [r0, #PM_DATA_SFRBU]
115 ldr r0, .pm_mode
126 ldr pmc, .pmc_base
145 ldr pmc, .pmc_base
146 ldr tmp2, .mckr_offset
147 ldr tmp1, [pmc, tmp2]
154 ldr r0, .sfrbu
159 ldr r0, .shdwc
166 ldr pmc, .pmc_base
167 ldr tmp2, .pm_mode
168 ldr tmp3, .mckr_offset
175 ldr tmp1, [pmc, tmp3]
184 ldr tmp1, [pmc, #AT91_CKGR_MOR]
190 ldr tmp1, [pmc, #AT91_PMC_SR]
196 ldr tmp1, [pmc, #AT91_CKGR_MOR]
203 2: ldr tmp1, [pmc, #AT91_PMC_SR]
215 ldr tmp1, [pmc, tmp3]
222 ldr tmp1, .saved_osc_status
227 ldr tmp1, [pmc, #AT91_CKGR_MOR]
234 3: ldr tmp1, [pmc, #AT91_PMC_SR]
239 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
253 ldr pmc, .pmc_base
254 ldr tmp2, .mckr_offset
257 ldr tmp1, [pmc, #AT91_PMC_SR]
263 ldr tmp1, [pmc, #AT91_CKGR_MOR]
270 1: ldr tmp1, [pmc, #AT91_PMC_SR]
275 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
284 ldr tmp1, [pmc, #AT91_CKGR_MOR]
291 ldr tmp1, [pmc, tmp2]
299 ldr tmp1, [pmc, #AT91_CKGR_MOR]
312 ldr tmp1, [pmc, #AT91_CKGR_MOR]
321 ldr tmp1, [pmc, tmp2]
328 ldr tmp1, [pmc, #AT91_CKGR_MOR]
337 ldr tmp1, [pmc, tmp2]
345 ldr tmp1, .saved_osc_status
350 ldr tmp1, [pmc, #AT91_CKGR_MOR]
357 4: ldr tmp1, [pmc, #AT91_PMC_SR]
366 ldr tmp1, .pmc_version
372 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT]
378 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
383 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
389 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
395 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
401 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
407 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
412 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
421 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
432 ldr tmp2, .saved_pllar
433 ldr tmp3, .pmc_version
439 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
445 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
449 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
456 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
462 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
473 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
479 3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
494 1: ldr tmp1, [pmc, #AT91_PMC_SR]
501 ldr pmc, .pmc_base
502 ldr tmp2, .mckr_offset
503 ldr tmp3, .pm_mode
506 ldr tmp1, [pmc, tmp2]
536 ldr pmc, .pmc_base
543 ldr tmp1, .mckr_offset
544 ldr tmp2, .saved_mckr
564 ldr r1, .memtype
565 ldr r2, .sramc_base
597 ldr r3, [r2, #AT91_DDRSDRC_MDR]
607 ldr r3, [r2, #AT91_DDRSDRC_LPR]
614 ldr r2, .sramc1_base
618 ldr r3, [r2, #AT91_DDRSDRC_MDR]
628 ldr r3, [r2, #AT91_DDRSDRC_LPR]
639 ldr r3, .saved_sam9_mdr
642 ldr r3, .saved_sam9_lpr
646 ldr r2, .sramc1_base
663 ldr r3, [r2, #AT91_SDRAMC_LPR]
670 ldr r3, .saved_sam9_lpr