Lines Matching defs:timing
116 struct dram_timing *timing;
568 struct device_node *np, uint32_t *timing)
578 (struct px30_ddr_dts_config_timing *)(timing +
626 struct device_node *np, uint32_t *timing)
635 (struct rk1808_ddr_dts_config_timing *)(timing +
687 struct device_node *np, uint32_t *timing)
696 init_timing = (struct share_params *)timing;
702 p = timing + DTS_PAR_OFFSET / 4;
714 (struct rk3128_ddr_dts_config_timing *)(timing +
727 struct device_node *np, uint32_t *timing)
734 p = timing + DTS_PAR_OFFSET / 4;
753 struct device_node *np, uint32_t *timing)
762 init_timing = (struct share_params *)timing;
768 p = timing + DTS_PAR_OFFSET / 4;
780 (struct rk3288_ddr_dts_config_timing *)(timing +
793 struct device_node *np, uint32_t *timing)
803 (struct rk3328_ddr_dts_config_timing *)(timing +
851 struct device_node *np, uint32_t *timing)
860 (struct rk1808_ddr_dts_config_timing *)(timing +
914 struct rk3368_dram_timing *timing = NULL;
920 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
921 if (!timing)
925 &timing->dram_spd_bin);
927 &timing->sr_idle);
929 &timing->pd_idle);
931 &timing->dram_dll_dis_freq);
933 &timing->phy_dll_dis_freq);
935 &timing->dram_odt_dis_freq);
937 &timing->phy_odt_dis_freq);
939 &timing->ddr3_drv);
941 &timing->ddr3_odt);
943 &timing->lpddr3_drv);
945 &timing->lpddr3_odt);
947 &timing->lpddr2_drv);
949 &timing->phy_clk_drv);
951 &timing->phy_cmd_drv);
953 &timing->phy_dqs_drv);
955 &timing->phy_odt);
957 &timing->ddr_2t);
959 devm_kfree(dev, timing);
963 return timing;
967 if (timing) {
968 devm_kfree(dev, timing);
969 timing = NULL;
972 return timing;
978 struct rk3399_dram_timing *timing = NULL;
984 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
985 if (!timing)
989 &timing->ddr3_speed_bin);
991 &timing->pd_idle);
993 &timing->sr_idle);
995 &timing->sr_mc_gate_idle);
997 &timing->srpd_lite_idle);
999 &timing->standby_idle);
1001 &timing->auto_lp_dis_freq);
1003 &timing->ddr3_dll_dis_freq);
1005 &timing->phy_dll_dis_freq);
1007 &timing->ddr3_odt_dis_freq);
1009 &timing->ddr3_drv);
1011 &timing->ddr3_odt);
1013 &timing->phy_ddr3_ca_drv);
1015 &timing->phy_ddr3_dq_drv);
1017 &timing->phy_ddr3_odt);
1019 &timing->lpddr3_odt_dis_freq);
1021 &timing->lpddr3_drv);
1023 &timing->lpddr3_odt);
1025 &timing->phy_lpddr3_ca_drv);
1027 &timing->phy_lpddr3_dq_drv);
1029 &timing->phy_lpddr3_odt);
1031 &timing->lpddr4_odt_dis_freq);
1033 &timing->lpddr4_drv);
1035 &timing->lpddr4_dq_odt);
1037 &timing->lpddr4_ca_odt);
1039 &timing->phy_lpddr4_ca_drv);
1041 &timing->phy_lpddr4_ck_cs_drv);
1043 &timing->phy_lpddr4_dq_drv);
1045 &timing->phy_lpddr4_odt);
1047 devm_kfree(dev, timing);
1051 return timing;
1055 if (timing) {
1056 devm_kfree(dev, timing);
1057 timing = NULL;
1060 return timing;
1630 * Get dram timing and pass it to arm trust firmware,
1632 * timing and to do dram initial.
1639 dev_err(dev, "send ddr timing timeout\n");
1641 dev_err(dev, "get ddr timing from dts error\n");
1693 u32 *timing;
1696 * Get dram timing and pass it to arm trust firmware,
1698 * timing and to do dram initial.
1702 timing = (u32 *)dram_timing;
1705 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,