Lines Matching refs:hw

226 static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw, int index, u8 value)

228 const struct grf_reg *reg = &hw->grf_regs[index];
232 regmap_write(hw->regmap_sys_grf, reg->offset, val);
236 static inline void write_grf_reg(struct csi2_dphy_hw *hw, int index, u8 value)
238 const struct grf_reg *reg = &hw->grf_regs[index];
242 regmap_write(hw->regmap_grf, reg->offset, val);
246 static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
248 const struct grf_reg *reg = &hw->grf_regs[index];
252 regmap_read(hw->regmap_grf, reg->offset, &val);
259 static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw, int index, u32 value)
261 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
265 writel(value, hw->hw_base_addr + reg->offset);
269 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw, int index, u32 value, u32 mask)
271 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
274 read_val = readl(hw->hw_base_addr + reg->offset);
277 writel(read_val, hw->hw_base_addr + reg->offset);
280 static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw, int index, u32 *value)
282 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
286 *value = readl(hw->hw_base_addr + reg->offset);
290 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane)
318 read_csi2_dphy_reg(hw, offset, &val);
320 write_csi2_dphy_reg(hw, offset, val);
474 static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
476 if (hw->rsts_bulk) {
477 reset_control_assert(hw->rsts_bulk);
482 if (hw->rsts_bulk) {
483 reset_control_deassert(hw->rsts_bulk);
489 struct csi2_dphy_hw *hw = dphy->dphy_hw;
502 if (hw->lane_mode == LANE_MODE_FULL) {
505 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0));
506 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
507 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
508 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
510 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
513 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0));
514 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
515 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
516 write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
518 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
526 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, GENMASK(sensor->lanes - 1, 0));
527 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
528 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
529 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
531 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_0_1);
533 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_0_1);
536 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
537 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
541 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, GENMASK(sensor->lanes - 1, 0));
542 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
543 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
544 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
546 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_2_3);
548 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_2_3);
551 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
552 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
556 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
557 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
558 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, GENMASK(sensor->lanes - 1, 0));
559 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
562 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
563 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
564 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, GENMASK(sensor->lanes - 1, 0));
565 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
577 struct csi2_dphy_hw *hw = dphy->dphy_hw;
578 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
584 mutex_lock(&hw->mutex);
592 read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
593 if (hw->lane_mode == LANE_MODE_FULL) {
607 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(0x06));
611 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
615 if (hw->lane_mode == LANE_MODE_FULL) {
616 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
617 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
619 read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
621 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
622 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
629 write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
633 if (hw->lane_mode == LANE_MODE_FULL) {
634 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
636 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
639 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
642 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
645 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
649 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
651 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
654 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
659 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
661 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
664 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
685 if (hw->lane_mode == LANE_MODE_FULL) {
686 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
688 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
691 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
694 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
697 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
701 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
702 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
703 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
707 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
708 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
709 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
713 atomic_inc(&hw->stream_cnt);
715 mutex_unlock(&hw->mutex);
722 struct csi2_dphy_hw *hw = dphy->dphy_hw;
724 if (atomic_dec_return(&hw->stream_cnt)) {
728 mutex_lock(&hw->mutex);
730 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
731 csi2_dphy_hw_do_reset(hw);
734 mutex_unlock(&hw->mutex);
739 static int csi_dcphy_wait_lane_prepare(struct csi2_dphy_hw *hw, int index)
744 read_csi2_dphy_reg(hw, index, &val);
747 read_csi2_dphy_reg(hw, index, &val);
760 struct csi2_dphy_hw *hw = dphy->dphy_hw;
761 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
777 mutex_lock(&hw->mutex);
779 write_grf_reg(hw, GRF_CPHY_MODE, 0x9);
782 if (hw->rsts_bulk) {
783 reset_control_assert(hw->rsts_bulk);
788 write_csi2_dphy_reg(hw, CSI2PHY_CLK_THS_SETTLE, 0x301);
789 write_csi2_dphy_reg(hw, CSI2PHY_S0C_GNR_CON1, 0x1450);
790 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D0_GNR_CON1, 0x1450);
791 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D1_GNR_CON1, 0x1450);
792 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D2_GNR_CON1, 0x1450);
793 write_csi2_dphy_reg(hw, CSI2PHY_S0D3_GNR_CON1, 0x1450);
810 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_THS_SETTLE, hsfreq, 0x1ff);
811 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_ERR_SOT_SYNC, sot_sync, 0xff);
814 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_THS_SETTLE, hsfreq, 0x1ff);
815 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_ERR_SOT_SYNC, sot_sync, 0xff);
818 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_THS_SETTLE, hsfreq, 0x1ff);
819 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_ERR_SOT_SYNC, sot_sync, 0xff);
822 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_THS_SETTLE, hsfreq, 0x1ff);
823 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_ERR_SOT_SYNC, sot_sync, 0xff);
827 write_csi2_dphy_reg(hw, CSI2PHY_CLK_LANE_ENABLE, BIT(0));
831 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE0_ENABLE, BIT(0));
834 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE1_ENABLE, BIT(0));
837 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE2_ENABLE, BIT(0));
840 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE3_ENABLE, BIT(0));
845 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_CLK_LANE_ENABLE)) {
852 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE0_ENABLE)) {
857 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE1_ENABLE)) {
862 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE2_ENABLE)) {
867 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE3_ENABLE)) {
872 if (hw->rsts_bulk) {
873 reset_control_deassert(hw->rsts_bulk);
875 atomic_inc(&hw->stream_cnt);
877 mutex_unlock(&hw->mutex);
881 if (hw->rsts_bulk) {
882 reset_control_deassert(hw->rsts_bulk);
884 mutex_unlock(&hw->mutex);
891 struct csi2_dphy_hw *hw = dphy->dphy_hw;
895 if (atomic_dec_return(&hw->stream_cnt)) {
899 mutex_lock(&hw->mutex);
901 write_csi2_dphy_reg(hw, CSI2PHY_CLK_LANE_ENABLE, 0);
904 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE0_ENABLE, 0);
907 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE1_ENABLE, 0);
910 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE2_ENABLE, 0);
913 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE3_ENABLE, 0);
918 mutex_unlock(&hw->mutex);
923 static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
925 hw->grf_regs = rk3568_grf_dphy_regs;
928 static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
930 hw->grf_regs = rk3588_grf_dphy_regs;
933 static void rk3588_csi2_dcphy_hw_individual_init(struct csi2_dphy_hw *hw)
935 hw->grf_regs = rk3588_grf_dcphy_regs;
974 .compatible = "rockchip,rk3568-csi2-dphy-hw",
977 .compatible = "rockchip,rk3588-csi2-dphy-hw",
980 .compatible = "rockchip,rk3588-csi2-dcphy-hw",
1049 dev_err(dev, "Can't find csi2 dphy hw addr!\n");
1064 dev_info(dev, "csi2 dphy hw probe successfully!\n");
1071 struct csi2_dphy_hw *hw = platform_get_drvdata(pdev);
1074 mutex_destroy(&hw->mutex);
1084 .name = "rockchip-csi2-dphy-hw",