Lines Matching refs:phys

101     phys_addr_t phys;

281 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);
284 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT));
285 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
286 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
287 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
289 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | RK3288_STROBE;
290 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
292 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
293 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~RK3288_STROBE);
294 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
299 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);
371 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);
374 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT));
375 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
376 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
377 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
379 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | RK3288_STROBE;
380 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
382 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
383 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~RK3288_STROBE);
384 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
389 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);
525 efuse->phys = res->start;