Lines Matching defs:efuse

110     /* setup efuse timing */

128     /* clear efuse timing */

143     struct rockchip_efuse_chip *efuse = context;

149     mutex_lock(&efuse->mutex);

151     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

153         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

168     rk1808_efuse_timing_init(efuse->base);

172                efuse->base + RK1808_AUTO_CTRL);

174         status = readl(efuse->base + RK1808_INT_STATUS);

179         out_value = readl(efuse->base + RK1808_DOUT);

180         writel(RK1808_INT_FINISH, efuse->base + RK1808_INT_STATUS);

187     rk1808_efuse_timing_deinit(efuse->base);

190     rk1808_efuse_timing_deinit(efuse->base);

191     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

193     mutex_unlock(&efuse->mutex);

200     struct rockchip_efuse_chip *efuse = context;

204     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

206         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

210     writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);

213         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3128_A_SHIFT)),

214                efuse->base + REG_EFUSE_CTRL);

215         writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3128_A_SHIFT),

216                efuse->base + REG_EFUSE_CTRL);

218         writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);

220         *buf++ = readb(efuse->base + REG_EFUSE_DOUT);

221         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);

226     writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);

228     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

235     struct rockchip_efuse_chip *efuse = context;

239     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

241         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

245     writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);

248         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT)),

249                efuse->base + REG_EFUSE_CTRL);

250         writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),

251                efuse->base + REG_EFUSE_CTRL);

253         writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);

255         *buf++ = readb(efuse->base + REG_EFUSE_DOUT);

256         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);

261     writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);

263     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

270     struct rockchip_efuse_chip *efuse = context;

275     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

277         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

281     sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);

284         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT));

285         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

286         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);

287         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

289         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | RK3288_STROBE;

290         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

292         *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);

293         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~RK3288_STROBE);

294         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

299     sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);

301     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

308     struct rockchip_efuse_chip *efuse = context;

314     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

316         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

320     /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */

335                efuse->base + RK3328_AUTO_CTRL);

337         status = readl(efuse->base + RK3328_INT_STATUS);

342         out_value = readl(efuse->base + RK3328_DOUT);

343         writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);

353     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

360     struct rockchip_efuse_chip *efuse = context;

365     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

367         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

371     sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);

374         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT));

375         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

376         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);

377         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

379         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | RK3288_STROBE;

380         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

382         *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);

383         wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~RK3288_STROBE);

384         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);

389     sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);

391     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

398     struct rockchip_efuse_chip *efuse = context;

404     ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);

406         dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");

421     writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, efuse->base + REG_EFUSE_CTRL);

424         writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),

425                efuse->base + REG_EFUSE_CTRL);

427         out_value = readl(efuse->base + REG_EFUSE_DOUT);

428         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), efuse->base + REG_EFUSE_CTRL);

436     writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);

443     clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);

449     .name = "rockchip-efuse",

458         .compatible = "rockchip,rk1808-efuse",

462         .compatible = "rockchip,rockchip-efuse",

466         .compatible = "rockchip,rk3066a-efuse",

470         .compatible = "rockchip,rk3128-efuse",

474         .compatible = "rockchip,rk3188-efuse",

478         .compatible = "rockchip,rk3228-efuse",

482         .compatible = "rockchip,rk3288-efuse",

486         .compatible = "rockchip,rk3288-secure-efuse",

490         .compatible = "rockchip,rk3328-efuse",

494         .compatible = "rockchip,rk3368-efuse",

498         .compatible = "rockchip,rk3399-efuse",

509     struct rockchip_efuse_chip *efuse;

519     efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip), GFP_KERNEL);

520     if (!efuse) {

525     efuse->phys = res->start;

526     efuse->base = devm_ioremap_resource(dev, res);

527     if (IS_ERR(efuse->base)) {

528         return PTR_ERR(efuse->base);

531     efuse->num_clks = devm_clk_bulk_get_all(dev, &efuse->clks);

532     if (efuse->num_clks < 1) {

536     mutex_init(&efuse->mutex);

538     efuse->dev = dev;

539     if (of_property_read_u32(dev->of_node, "rockchip,efuse-size", &econfig.size)) {

543     econfig.priv = efuse;

544     econfig.dev = efuse->dev;

554             .name = "rockchip-efuse",

565         pr_err("failed to register efuse driver\n");