1root { 2 platform { 3 template codec_controller { 4 match_attr = ""; 5 serviceName = ""; 6 codecDaiName = ""; 7 } 8 controller_0x120c1030 :: codec_controller { 9 match_attr = "hdf_codec_driver"; 10 serviceName = "codec_service_0"; 11 codecDaiName = "codec_dai"; 12 13 idInfo { 14 chipName = "hi3516"; 15 chipIdRegister = 0x113c0000; 16 chipIdSize = 0x1000; 17 } 18 19 regConfig { 20 /* reg, value */ 21 initSeqConfig = [ 22 0x14, 0x04000002, 23 0x18, 0xFD200004, 24 0x1C, 0x00180018, 25 0x20, 0x83830028, 26 0x24, 0x00005C5C, 27 0x28, 0x00130000, 28 0x30, 0xFF035A00, 29 0x34, 0x08000001, 30 0x38, 0x06062424, 31 0x3C, 0x1E1EC001, 32 0x14, 0x04000002 33 ]; 34 35 /* reg: register address 36 rreg: register address 37 shift: shift bits 38 rshift: rshift bits 39 min: min value 40 max: max value 41 mask: mask of value 42 invert: enum InvertVal 0-uninvert 1-invert 43 value: value 44 */ 45 ctrlParamsSeqConfig = [ 46 0x2004, 0x2004, 8, 8, 0x28, 0x7F, 0x7F, 0, 0, //"Main Playback Volume" 47 0x3c, 0x3c, 24, 24, 0x0, 0x57, 0x7F, 1, 0, //"Main Capture Volume" 48 0x38, 0x38, 31, 31, 0x0, 0x1, 0x1, 0, 0, //"Playback Mute" 49 0x3c, 0x3c, 31, 31, 0x0, 0x1, 0x1, 0, 0, //"Capture Mute" 50 0x20, 0x20, 16, 16, 0x0, 0xF, 0x1F, 0, 0, //"Mic Left Gain" 51 0x20, 0x20, 24, 24, 0x0, 0xF, 0x1F, 0, 0, //"Mic Right Gain" 52 0x2000, 0x2000, 16, 16, 0x0, 0x7, 0x7, 0, 0, //"Render Channel Mode" 53 0x1000, 0x1000, 16, 16, 0x0, 0x7, 0x7, 0, 0 //"Capture Channel Mode" 54 ]; 55 56 controlsConfig = [ 57 /* 58 "Master Playback Volume", 59 "Master Capture Volume", 60 "Playback Mute", 61 "Capture Mute", 62 "Mic Left Gain", 63 "Mic Right Gain", 64 "External Codec Enable", 65 "Internally Codec Enable", 66 "Render Channel Mode", 67 "Capture Channel Mode" 68 */ 69 70 /*array index, iface, enable*/ 71 0, 0, 0, 72 1, 1, 1, 73 2, 0, 1, 74 3, 1, 1, 75 4, 2, 1, 76 5, 2, 1, 77 8, 6, 0, 78 9, 6, 0, 79 ]; 80 81 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 82 daiStartupSeqConfig = [ 83 0x24, 0x24, 11, 11, 0x0, 0x1, 0x1, 0, 0x1 // adc_tune_En09 84 ]; 85 86 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 87 daiParamsSeqConfig = [ 88 0x30, 0x30, 13, 13, 0x0, 0x1F, 0x1F, 0, 0x0, // i2s_frequency 89 0x1C, 0x1C, 6, 6, 0x0, 0x3, 0x3, 0, 0x0, // adc_mode_sel 90 0x30, 0x30, 22, 22, 0x0, 0x3, 0x3, 0, 0x0, // i2s_datawith 91 ]; 92 93 ctrlSapmParamsSeqConfig = [ 94 0x20, 0x20, 23, 23, 0x0, 0x1, 0x1, 0, 0, //LPGA MIC 0 -- connect MIC 95 0x20, 0x20, 31, 31, 0x0, 0x1, 0x1, 0, 0, //RPGA MIC 0 -- connect MIC 96 0x30, 0x30, 27, 27, 0x0, 0x1, 0x1, 0, 0, //dacl to dacr mixer 97 0x30, 0x30, 26, 26, 0x0, 0x1, 0x1, 0, 0 //dacr to dacl mixer 98 ]; 99 100 /* index = "ADCL", "ADCR", "DACL", "DACR", "LPGA", "RPGA", "SPKL", "SPKR", "MIC"*/ 101 sapmComponent = [ 102 10, 0, 0x20, 0x1, 15, 1, 0, 0, //ADCL 103 10, 1, 0x20, 0x1, 14, 1, 0, 0, //ADCR 104 11, 2, 0x14, 0x1, 11, 1, 0, 0, //DACL 105 11, 3, 0x14, 0x1, 12, 1, 0, 0, //DACR 106 8, 4, 0x20, 0x1, 13, 1, 1, 1, //LPGA 107 8, 5, 0x20, 0x1, 12, 1, 2, 1, //RPGA 108 15, 6, 0, 0x1, 0, 0, 3, 1, //SPKL 109 15, 7, 0, 0x1, 0, 0, 4, 1, //SPKR 110 0, 8, 0, 0x1, 0, 0, 0, 0 //MIC 111 ]; 112 113 /*array index, iface, enable*/ 114 sapmConfig = [ 115 0, 5, 1, 116 1, 5, 1, 117 2, 0, 1, 118 3, 0, 1 119 ]; 120 } 121 } 122 controller_0x120c1031 :: codec_controller { 123 match_attr = "hdf_codec_driver_ex"; 124 serviceName = "codec_service_1"; 125 codecDaiName = "accessory_dai"; 126 127 regConfig { 128 /* regAddr: register address 129 regValue: config register value 130 mask: mask of value 131 shift: shift bits 132 max: max value 133 min: min value 134 invert: enum Tfa9879InvertVal 0-uninvert 1-invert 135 */ 136 137 /* reg, value */ 138 /* regAddr, regValue, mask, shift, max, min, invert, opsType */ 139 /* reg, rreg, shift, value, min, max, mask, invert */ 140 resetSeqConfig = [ 141 0x00, 0x0 142 ]; 143 144 /* reg, value */ 145 initSeqConfig = [ 146 0x00, 0x0001, 147 0x01, 0x0a18, 148 0x02, 0x0007, 149 0x03, 0x0a18, 150 0x04, 0x0007, 151 0x05, 0x59DD, 152 0x06, 0xC63E, 153 0x07, 0x651A, 154 0x08, 0xE53E, 155 0x09, 0x4616, 156 0x0A, 0xD33E, 157 0x0B, 0x4DF3, 158 0x0C, 0xEA3E, 159 0x0D, 0x5EE0, 160 0x0E, 0xF93E, 161 0x0F, 0x0008, 162 0x10, 0x92BA, 163 0x11, 0x12A5, 164 0x12, 0x0004, 165 0x13, 0x1031, 166 0x14, 0x0000 167 ]; 168 169 /* reg: register address 170 rreg: register address 171 shift: shift bits 172 rshift: rshift bits 173 min: min value 174 max: max value 175 mask: mask of value 176 invert: enum InvertVal 0-uninvert 1-invert 177 value: value 178 */ 179 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 180 ctrlParamsSeqConfig = [ 181 0x13, 0x13, 0, 0, 0x0, 0xBC, 0xFF, 1, 0x0, // output volume 182 0x14, 0x14, 9, 9, 0x0, 0x1, 0x1, 0, 0x0, // output mute 183 0x01, 0x01, 10, 10, 0x0, 0x3, 0x3, 0, 0x0 // output channel 184 ]; 185 186 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 187 daiStartupSeqConfig = [ 188 0x00, 0x00, 0, 0, 0x0, 0xF, 0xF, 0, 0x9 // work 189 ]; 190 191 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 192 daiParamsSeqConfig = [ 193 0x01, 0x01, 6, 6, 0x0, 0xF, 0xF, 0, 0x0, // i2s_frequency 194 0x01, 0x01, 3, 3, 0x0, 0x7, 0x7, 0, 0x0, // i2s_format 195 0x01, 0x01, 10, 10, 0x0, 0x3, 0x3, 0, 0x0 // i2s_channel 196 ]; 197 198 controlsConfig = [ 199 /* 200 "Master Playback Volume", 201 "Playback Mute", 202 "Render Channel Mode" 203 */ 204 /*array index, iface, enable*/ 205 0, 0, 1, 206 2, 0, 1, 207 8, 6, 1 208 ]; 209 } 210 } 211 } 212} 213