10b966c5eSopenharmony_ciroot { 20b966c5eSopenharmony_ci platform { 30b966c5eSopenharmony_ci template dma_controller { 40b966c5eSopenharmony_ci match_attr = ""; 50b966c5eSopenharmony_ci serviceName = ""; 60b966c5eSopenharmony_ci } 70b966c5eSopenharmony_ci controller_0x120c1010 :: dma_controller { 80b966c5eSopenharmony_ci match_attr = "hdf_dma_driver"; 90b966c5eSopenharmony_ci serviceName = "dma_service_0"; 100b966c5eSopenharmony_ci 110b966c5eSopenharmony_ci idInfo { 120b966c5eSopenharmony_ci chipName = "/i2s@fe410000"; 130b966c5eSopenharmony_ci chipIdRegister = 0xfe410000; 140b966c5eSopenharmony_ci chipIdSize = 0x1000; 150b966c5eSopenharmony_ci } 160b966c5eSopenharmony_ci regConfig { 170b966c5eSopenharmony_ci /* reg: register address 180b966c5eSopenharmony_ci rreg: register address 190b966c5eSopenharmony_ci shift: shift bits 200b966c5eSopenharmony_ci rshift: rshift bits 210b966c5eSopenharmony_ci min: min value 220b966c5eSopenharmony_ci max: max value 230b966c5eSopenharmony_ci mask: mask of value 240b966c5eSopenharmony_ci invert: enum InvertVal 0-uninvert 1-invert 250b966c5eSopenharmony_ci value: value 260b966c5eSopenharmony_ci 270b966c5eSopenharmony_ci reg, rreg, shift, rshift, min, max, mask, invert value 280b966c5eSopenharmony_ci */ 290b966c5eSopenharmony_ci daiStartupSeqConfig = [ 300b966c5eSopenharmony_ci 0x00, 0x00, 0, 0, 0, 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x0, //Transmit Operation Init 310b966c5eSopenharmony_ci ]; 320b966c5eSopenharmony_ci } 330b966c5eSopenharmony_ci } 340b966c5eSopenharmony_ci controller_0x120c1011 :: dma_controller { 350b966c5eSopenharmony_ci match_attr = "hdf_hdmi_dma_driver"; 360b966c5eSopenharmony_ci serviceName = "hdmi_dma_service_0"; 370b966c5eSopenharmony_ci 380b966c5eSopenharmony_ci idInfo { 390b966c5eSopenharmony_ci chipName = "/i2s@fe400000"; 400b966c5eSopenharmony_ci chipIdRegister = 0xfe400000; 410b966c5eSopenharmony_ci chipIdSize = 0x1000; 420b966c5eSopenharmony_ci } 430b966c5eSopenharmony_ci regConfig { 440b966c5eSopenharmony_ci /* reg: register address 450b966c5eSopenharmony_ci rreg: register address 460b966c5eSopenharmony_ci shift: shift bits 470b966c5eSopenharmony_ci rshift: rshift bits 480b966c5eSopenharmony_ci min: min value 490b966c5eSopenharmony_ci max: max value 500b966c5eSopenharmony_ci mask: mask of value 510b966c5eSopenharmony_ci invert: enum InvertVal 0-uninvert 1-invert 520b966c5eSopenharmony_ci value: value 530b966c5eSopenharmony_ci 540b966c5eSopenharmony_ci reg, rreg, shift, rshift, min, max, mask, invert value 550b966c5eSopenharmony_ci */ 560b966c5eSopenharmony_ci daiStartupSeqConfig = [ 570b966c5eSopenharmony_ci 0x00, 0x00, 0, 0, 0, 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x0, //Transmit Operation Init 580b966c5eSopenharmony_ci ]; 590b966c5eSopenharmony_ci } 600b966c5eSopenharmony_ci } 610b966c5eSopenharmony_ci } 620b966c5eSopenharmony_ci} 63