1/******************************************************************************
2 *
3 *  Copyright (C) 2009-2012 Broadcom Corporation
4 *
5 *  Licensed under the Apache License, Version 2.0 (the "License");
6 *  you may not use this file except in compliance with the License.
7 *  You may obtain a copy of the License at:
8 *
9 *  http://www.apache.org/licenses/LICENSE-2.0
10 *
11 *  Unless required by applicable law or agreed to in writing, software
12 *  distributed under the License is distributed on an "AS IS" BASIS,
13 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 *  See the License for the specific language governing permissions and
15 *  limitations under the License.
16 *
17 ******************************************************************************/
18
19/******************************************************************************
20 *
21 *  Filename:      bt_vendor_brcm.h
22 *
23 *  Description:   A wrapper header file of bt_vendor_lib.h
24 *
25 *                 Contains definitions specific for interfacing with Broadcom
26 *                 Bluetooth chipsets
27 *
28 ******************************************************************************/
29
30#ifndef BT_VENDOR_BRCM_H
31#define BT_VENDOR_BRCM_H
32
33#include "bt_vendor_lib.h"
34
35/******************************************************************************
36**  Constants & Macros
37******************************************************************************/
38
39#ifndef FALSE
40#define FALSE 0
41#endif
42
43#ifndef TRUE
44#define TRUE (!FALSE)
45#endif
46
47#ifndef VENDOR_LIB_RUNTIME_TUNING_ENABLED
48#define VENDOR_LIB_RUNTIME_TUNING_ENABLED FALSE
49#endif
50
51/* Run-time configuration file */
52#ifndef VENDOR_LIB_CONF_FILE
53#define VENDOR_LIB_CONF_FILE "/vendor/etc/bluetooth/bt_vendor.conf"
54#endif
55
56/* Device port name where Bluetooth controller attached */
57#ifndef BLUETOOTH_UART_DEVICE_PORT
58#define BLUETOOTH_UART_DEVICE_PORT "/dev/ttyS8" /* maguro */
59#endif
60
61/* Location of firmware patch files */
62#ifndef FW_PATCHFILE_LOCATION
63#define FW_PATCHFILE_LOCATION "/vendor/etc/firmware/" /* maguro */
64#endif
65
66#ifndef UART_TARGET_BAUD_RATE
67#define UART_TARGET_BAUD_RATE 3000000
68#endif
69
70/* The millisecond delay pauses on HCI transport after firmware patches
71 * were downloaded. This gives some time for firmware to restart with
72 * patches before host attempts to send down any HCI commands.
73 *
74 * Note: It has been discovered that BCM43241B0 needs at least 200ms
75 * settlement delay in here. Without the delay, a Hardware Error event
76 * from BCM43241B0 had been seen in HCI upstream path right after the
77 * host sent the HCI_VSC_SET_BDADDR commad to the controller at higher
78 * baud.
79 */
80#ifndef FW_PATCH_SETTLEMENT_DELAY_MS
81#define FW_PATCH_SETTLEMENT_DELAY_MS 0
82#endif
83
84#ifndef USERIAL_VENDOR_SET_BAUD_DELAY_US
85#define USERIAL_VENDOR_SET_BAUD_DELAY_US 0
86#endif
87
88#ifndef FW_AUTO_DETECTION
89#define FW_AUTO_DETECTION FALSE
90#endif
91
92/* The Bluetooth Device Address source switch:
93 *
94 * -FALSE- (default value)
95 *  Get the factory BDADDR from device's file system. Normally the BDADDR is
96 *  stored in the location pointed by the PROPERTY_BT_BDADDR_PATH (defined in
97 *  btif_common.h file) property.
98 *
99 * -TRUE-
100 *  If the Bluetooth Controller has equipped with a non-volatile memory (such
101 *  as BCM4330's OTP memory), the factory BDADDR can be stored in there and
102 *  retrieved by the stack while enabling BT.
103 *  !!! WARNING !!! Make sure that the OTP feature has been enabled in the
104 *  firmware patchram (.hcd) file.
105 */
106#ifndef USE_CONTROLLER_BDADDR
107#define USE_CONTROLLER_BDADDR FALSE
108#endif
109
110/* sleep mode
111
112    0: disable
113    1: UART with Host wake/BT wake out of band signals
114*/
115#ifndef LPM_SLEEP_MODE
116#define LPM_SLEEP_MODE 0
117#endif
118
119/* Host Stack Idle Threshold in 300ms or 25ms
120  In sleep mode 1, this is the number of firmware loops executed with no
121    action before the Host wake line is deasserted. action includes HCI
122    traffic excluding certain sleep mode commands and the presence of SCO
123    connections if the "Allow Host Sleep During SCO" flag is not set to 1.
124    Each count of this parameter is roughly equivalent to 300ms or 25ms.
125*/
126#ifndef LPM_IDLE_THRESHOLD
127#define LPM_IDLE_THRESHOLD 1
128#endif
129
130/* Host Controller Idle Threshold in 300ms or 25ms
131
132    This is the number of firmware loops executed with no action before the
133    HC is considered idle. Depending on the mode, HC may then attempt to sleep.
134    Action includes HCI traffic excluding certain sleep mode commands and
135    the presence of ACL/SCO connections.
136*/
137#ifndef LPM_HC_IDLE_THRESHOLD
138#define LPM_HC_IDLE_THRESHOLD 1
139#endif
140
141/* BT_WAKE Polarity - 0=Active Low, 1= Active High */
142#ifndef LPM_BT_WAKE_POLARITY
143#define LPM_BT_WAKE_POLARITY 1 /* maguro */
144#endif
145
146/* HOST_WAKE Polarity - 0=Active Low, 1= Active High */
147#ifndef LPM_HOST_WAKE_POLARITY
148#define LPM_HOST_WAKE_POLARITY 1 /* maguro */
149#endif
150
151/* LPM_ALLOW_HOST_SLEEP_DURING_SCO
152
153    When this flag is set to 0, the host is not allowed to sleep while
154    an SCO is active. In sleep mode 1, the device will keep the host
155    wake line asserted while an SCO is active.
156    When this flag is set to 1, the host can sleep while an SCO is active.
157    This flag should only be set to 1 if SCO traffic is directed to the PCM
158    interface.
159*/
160#ifndef LPM_ALLOW_HOST_SLEEP_DURING_SCO
161#define LPM_ALLOW_HOST_SLEEP_DURING_SCO 1
162#endif
163
164/* LPM_COMBINE_SLEEP_MODE_AND_LPM
165
166    In Mode 0, always set byte 7 to 0. In sleep mode 1, device always
167    requires permission to sleep between scans / periodic inquiries regardless
168    of the setting of this byte. In sleep mode 1, if byte is set, device must
169    have "permission" to sleep during the low power modes of sniff, hold, and
170    park. If byte is not set, device can sleep without permission during these
171    modes. Permission to sleep in Mode 1 is obtained if the BT_WAKE signal is
172    not asserted.
173*/
174#ifndef LPM_COMBINE_SLEEP_MODE_AND_LPM
175#define LPM_COMBINE_SLEEP_MODE_AND_LPM 1
176#endif
177
178/* LPM_ENABLE_UART_TXD_TRI_STATE
179
180    When set to 0, the device will not tristate its UART TX line before going
181    to sleep.
182    When set to 1, the device will tristate its UART TX line before going to
183    sleep.
184*/
185#ifndef LPM_ENABLE_UART_TXD_TRI_STATE
186#define LPM_ENABLE_UART_TXD_TRI_STATE 0
187#endif
188
189/* LPM_PULSED_HOST_WAKE
190*/
191#ifndef LPM_PULSED_HOST_WAKE
192#define LPM_PULSED_HOST_WAKE 0
193#endif
194
195/* LPM_IDLE_TIMEOUT_MULTIPLE
196
197    The multiple factor of host stack idle threshold in 300ms/25ms
198*/
199#ifndef LPM_IDLE_TIMEOUT_MULTIPLE
200#define LPM_IDLE_TIMEOUT_MULTIPLE 10
201#endif
202
203/* BT_WAKE_VIA_USERIAL_IOCTL
204
205    Use userial ioctl function to control BT_WAKE signal
206*/
207#ifndef BT_WAKE_VIA_USERIAL_IOCTL
208#define BT_WAKE_VIA_USERIAL_IOCTL FALSE
209#endif
210
211/* BT_WAKE_USERIAL_LDISC
212
213    Use line discipline if the BT_WAKE control is in line discipline
214*/
215#ifndef BT_WAKE_USERIAL_LDISC
216#define BT_WAKE_USERIAL_LDISC FALSE
217#endif
218
219/* BT_WAKE_VIA_PROC
220
221    LPM & BT_WAKE control through PROC nodes
222*/
223#ifndef BT_WAKE_VIA_PROC
224#define BT_WAKE_VIA_PROC FALSE
225#endif
226
227#ifndef BT_WAKE_VIA_PROC_NOTIFY_DEASSERT
228#define BT_WAKE_VIA_PROC_NOTIFY_DEASSERT FALSE
229#endif
230
231/* N_BRCM_HCI
232
233    UART ioctl line discipline
234*/
235#ifndef N_BRCM_HCI
236#define N_BRCM_HCI 25
237#endif
238
239/* SCO_CFG_INCLUDED
240
241    Do SCO configuration by default. If the firmware patch had been embedded
242    with desired SCO configuration, set this FALSE to bypass configuration
243    from host software.
244*/
245#ifndef SCO_CFG_INCLUDED
246#define SCO_CFG_INCLUDED TRUE
247#endif
248
249#ifndef SCO_USE_I2S_INTERFACE
250#define SCO_USE_I2S_INTERFACE FALSE
251#endif
252
253#define SCO_I2SPCM_PARAM_IF_MODE 0
254#define SCO_I2SPCM_PARAM_IF_ROLE 1
255#define SCO_I2SPCM_PARAM_IF_SAMPLE_RATE 2
256#define SCO_I2SPCM_PARAM_IF_CLOCK_RATE 3
257#define SCO_I2SPCM_PARAM_SIZE 4
258
259/* SCO_WBS_SAMPLE_RATE
260    0 : 8K
261    1 : 16K
262    2 : 4K
263 This macro is used for setting WBS sampling rate for a SCO connection
264 If the mobile network supports WBS, we need to use 16KHz as default
265 but if the platform doesn't support 16KHz, the sample rate can be
266 overriden to 8KHz by setting this to 0.
267*/
268#ifndef SCO_WBS_SAMPLE_RATE
269#define SCO_WBS_SAMPLE_RATE 1
270#endif
271
272/* SCO_I2SPCM_IF_MODE - 0=Disable, 1=Enable */
273#ifndef SCO_I2SPCM_IF_MODE
274#define SCO_I2SPCM_IF_MODE 1
275#endif
276
277/* SCO_I2SPCM_IF_ROLE - 0=Slave, 1=Master */
278#ifndef SCO_I2SPCM_IF_ROLE
279#define SCO_I2SPCM_IF_ROLE 1
280#endif
281
282/* SCO_I2SPCM_IF_SAMPLE_RATE
283
284    0 : 8K
285    1 : 16K
286    2 : 4K
287*/
288#ifndef SCO_I2SPCM_IF_SAMPLE_RATE
289#define SCO_I2SPCM_IF_SAMPLE_RATE 0
290#endif
291
292/* SCO_I2SPCM_IF_CLOCK_RATE
293
294    0 : 128K
295    1 : 256K
296    2 : 512K
297    3 : 1024K
298    4 : 2048K
299*/
300#ifndef SCO_I2SPCM_IF_CLOCK_RATE
301#define SCO_I2SPCM_IF_CLOCK_RATE 1
302#endif
303
304/* SCO_I2SPCM_IF_CLOCK_RATE4WBS
305
306    0 : 128K
307    1 : 256K
308    2 : 512K
309    3 : 1024K
310    4 : 2048K
311*/
312#ifndef SCO_I2SPCM_IF_CLOCK_RATE4WBS
313#define SCO_I2SPCM_IF_CLOCK_RATE4WBS 2
314#endif
315
316#define SCO_PCM_PARAM_ROUTING 0
317#define SCO_PCM_PARAM_IF_CLOCK_RATE 1
318#define SCO_PCM_PARAM_IF_FRAME_TYPE 2
319#define SCO_PCM_PARAM_IF_SYNC_MODE 3
320#define SCO_PCM_PARAM_IF_CLOCK_MODE 4
321#define SCO_PCM_PARAM_SIZE 5
322
323/* SCO_PCM_ROUTING
324
325    0 : PCM
326    1 : Transport
327    2 : Codec
328    3 : I2S
329*/
330#ifndef SCO_PCM_ROUTING
331#define SCO_PCM_ROUTING 0
332#endif
333
334/* SCO_PCM_IF_CLOCK_RATE
335
336    NOTICE: suggested to be consistent with SCO_I2SPCM_IF_CLOCK_RATE
337
338    0 : 128K
339    1 : 256K
340    2 : 512K
341    3 : 1024K
342    4 : 2048K
343*/
344#ifndef SCO_PCM_IF_CLOCK_RATE
345#define SCO_PCM_IF_CLOCK_RATE 4
346#endif
347
348/* SCO_PCM_IF_FRAME_TYPE - 0=Short, 1=Long */
349#ifndef SCO_PCM_IF_FRAME_TYPE
350#define SCO_PCM_IF_FRAME_TYPE 0
351#endif
352
353/* SCO_PCM_IF_SYNC_MODE
354
355    NOTICE: in most usage cases the value will be the same as
356            SCO_PCM_IF_CLOCK_MODE setting
357
358    0 : Slave
359    1 : Master
360*/
361#ifndef SCO_PCM_IF_SYNC_MODE
362#define SCO_PCM_IF_SYNC_MODE 0
363#endif
364
365/* SCO_PCM_IF_CLOCK_MODE
366
367    NOTICE: suggested to be consistent with SCO_I2SPCM_IF_ROLE
368
369    0 : Slave
370    1 : Master
371*/
372#ifndef SCO_PCM_IF_CLOCK_MODE
373#define SCO_PCM_IF_CLOCK_MODE 0
374#endif
375
376#define PCM_DATA_FORMAT_PARAM_SIZE 5
377
378/* PCM_DATA_FMT_SHIFT_MODE
379
380    0 : MSB first
381    1 : LSB first
382*/
383#ifndef PCM_DATA_FMT_SHIFT_MODE
384#define PCM_DATA_FMT_SHIFT_MODE 0
385#endif
386
387/* PCM_DATA_FMT_FILL_BITS
388
389    Specifies the value with which to fill unused bits
390    if Fill_Method is set to programmable
391*/
392#ifndef PCM_DATA_FMT_FILL_BITS
393#define PCM_DATA_FMT_FILL_BITS 0
394#endif
395
396/* PCM_DATA_FMT_FILL_METHOD
397
398    0 : 0's
399    1 : 1's
400    2 : Signed
401    3 : Programmable
402*/
403#ifndef PCM_DATA_FMT_FILL_METHOD
404#define PCM_DATA_FMT_FILL_METHOD 3
405#endif
406
407/* PCM_DATA_FMT_FILL_NUM
408
409    Specifies the number of bits to be filled
410*/
411#ifndef PCM_DATA_FMT_FILL_NUM
412#define PCM_DATA_FMT_FILL_NUM 0
413#endif
414
415/* PCM_DATA_FMT_JUSTIFY_MODE
416
417    0 : Left justify (fill data shifted out last)
418    1 : Right justify (fill data shifted out first)
419*/
420#ifndef PCM_DATA_FMT_JUSTIFY_MODE
421#define PCM_DATA_FMT_JUSTIFY_MODE 0
422#endif
423
424/* HW_END_WITH_HCI_RESET
425
426    Sample code implementation of sending a HCI_RESET command during the epilog
427    process. It calls back to the callers after command complete of HCI_RESET
428    is received.
429*/
430#ifndef HW_END_WITH_HCI_RESET
431#define HW_END_WITH_HCI_RESET TRUE
432#endif
433
434#define BD_ADDR_LEN 6
435#define BT_VENDOR_TIME_RAIDX 1000
436/******************************************************************************
437**  Extern variables and functions
438******************************************************************************/
439
440extern bt_vendor_callbacks_t *bt_vendor_cbacks;
441/** audio (SCO) state changes triggering VS commands for configuration */
442typedef struct {
443    uint16_t handle;
444    uint16_t peer_codec;
445    uint16_t state;
446} bt_vendor_op_audio_state_t;
447
448extern int hw_set_audio_state(bt_vendor_op_audio_state_t *p_state);
449extern uint8_t vnd_local_bd_addr[BD_ADDR_LEN];
450
451extern void hw_process_event(HC_BT_HDR *);
452
453#endif /* BT_VENDOR_BRCM_H */
454