15db71995Sopenharmony_ci// 25db71995Sopenharmony_ci// Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 35db71995Sopenharmony_ci// 45db71995Sopenharmony_ci// Licensed under the Apache License, Version 2.0 (the "License"); 55db71995Sopenharmony_ci// you may not use this file except in compliance with the License. 65db71995Sopenharmony_ci// You may obtain a copy of the License at 75db71995Sopenharmony_ci// 85db71995Sopenharmony_ci// http://www.apache.org/licenses/LICENSE-2.0 95db71995Sopenharmony_ci// 105db71995Sopenharmony_ci// Unless required by applicable law or agreed to in writing, software 115db71995Sopenharmony_ci// distributed under the License is distributed on an "AS IS" BASIS, 125db71995Sopenharmony_ci// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 135db71995Sopenharmony_ci// See the License for the specific language governing permissions and 145db71995Sopenharmony_ci// limitations under the License. 155db71995Sopenharmony_ci// 165db71995Sopenharmony_ci 175db71995Sopenharmony_ci.text 185db71995Sopenharmony_ci.global sample 195db71995Sopenharmony_ci.set PHYS_DEV_OFFSET_INST_DISPATCH, 10 205db71995Sopenharmony_ci.set PTR_SIZE, 4 215db71995Sopenharmony_cisample: 225db71995Sopenharmony_ci mov x1, (PHYS_DEV_OFFSET_INST_DISPATCH + (PTR_SIZE * 4)) 235db71995Sopenharmony_ci ldr x0, [x0, x1] 24