xref: /third_party/vixl/test/aarch64/traces/sim-fjcvtzs-wd-trace-aarch64.h

// Copyright 2015, VIXL authors
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//
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// modification, are permitted provided that the following conditions are met:
//
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//     this list of conditions and the following disclaimer in the documentation
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//     specific prior written permission.
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_FJCVTZS_WD_TRACE_AARCH64_H_
#define VIXL_SIM_FJCVTZS_WD_TRACE_AARCH64_H_

const int32_t kExpected_fjcvtzs_wd[] = {
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(10),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(10),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(1),
  INT32_C(2),
  INT32_C(3),
  -INT32_C(1450744509),
  -INT32_C(4),
  -INT32_C(3),
  -INT32_C(2),
  -INT32_C(1),
  INT32_C(0),
  INT32_C(0),
  INT32_C(1),
  INT32_C(1),
  -INT32_C(725372255),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(1),
  -INT32_C(1),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(362686128),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(2),
  -INT32_C(3),
  INT32_C(1450744509),
  INT32_C(4),
  INT32_C(3),
  INT32_C(2),
  INT32_C(1),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  INT32_C(725372255),
  INT32_C(2),
  INT32_C(2),
  INT32_C(1),
  INT32_C(1),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(362686128),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  -INT32_C(2048),
  INT32_C(0),
  INT32_C(1024),
  -INT32_C(1024),
  INT32_C(0),
  -INT32_C(2048),
  INT32_C(0),
  INT32_C(2147483647),
  INT32_C(2147483647),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647),
  -INT32_C(2147483647),
  -INT32_C(2147483647),
  -INT32_C(2147483647),
  INT32_C(2147483645),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  -INT32_C(3),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
};
const unsigned kExpectedCount_fjcvtzs_wd = 207;

#endif  // VIXL_SIM_FJCVTZS_WD_TRACE_AARCH64_H_