xref: /third_party/vixl/test/aarch32/config/rd-rn-rm.json (revision b8021494)

// Copyright 2016, VIXL authors
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// Test description for instructions of the following form:
//   MNEMONIC <Rd>, <Rn>, <Rm>

{
  "mnemonics" : [
    "Crc32b",  // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1
               // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1
    "Crc32cb", // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1
               // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1
    "Crc32ch", // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1
               // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1
    "Crc32cw", // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1
               // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1
    "Crc32h",  // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1
               // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; T1
    "Crc32w"   // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; A1
               // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; T1
  ],
  "description" : {
    "operands": [
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "rn",
        "type": "AllRegistersButPC"
      },
      {
        "name": "rm",
        "type": "AllRegistersButPC"
      }
    ],
    "inputs": [
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      },
      {
        "name": "rm",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Registers",
          "operands": [
            "rd", "rn", "rm"
          ],
          "operand-limit": 500
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "RnIsRm",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rn == rm",
          "operand-limit": 10,
          "input-filter": "rn == rm",
          "input-limit": 200
        },
        {
          "name": "RnIsNotRm",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rn != rm",
          "operand-limit": 10,
          "input-filter": "rn != rm",
          "input-limit": 200
        }
      ]
    }
  ]
}